Let's take this one step at a time. You seem to be confused about the term "clock skew". Clock skew is the amount of time by which the clocks as seen by two different flip-flops can be different.
For example, if you take the clock at FF2 as your reference, the rising edge of the clock at FF3 might occur anywhere from 0.2 ns before the same edge at FF2 to 0.2 ns after that edge.
What this means is that from the "point of view" of FF2, the setup and hold times of FF3 have been "blurred" or expanded by ±0.2 ns, and you now have to think of them as being 0.7 and 1.2 ns worst-case, respectively.
EDIT: So, the maximum delay for C is the clock period (10 ns) minus the quantity (FF3 setup time (0.5 ns) plus the clock skew (0.2 ns) plus the maximum delay for S (2.0 ns) plus the maximum FF2 clock-to-output delay (0.2 ns)), or 10 – (0.5 + 0.2 + 2.0 + 0.2) = 7.1 ns.
Similarly, the minimum delay for C is determined by the hold-time requirement of FF3. You add together the FF3 hold time plus the clock skew, and subtract out the minimum FF2 clock-to-output delay and the minimum delay through S. This works out to (1.0 + 0.2) – (0.2 + 0.5) = 0.5 ns.
From my textbook, Digital Design and Computer Architecture, Harris and Harris, pg. 88
An important note
When you are attempting to find the propagation delay of a combinational circuit with multiple elements, you must add the propagation delay through the critical path.
However when you are attempting to find the contamination delay of a combinational circuit with multiple elements, you must add the contamination delay through the shortest path.
That much is probably obvious to you.
Actually, it sounds to me like you are referring to contamination delay. You said contamination delay is the amount of time measured after an input changes that the output remains valid. If you mean the previous output, then yes, because that means the same thing as until the output begins changing to the new value.
Addition
About your question as to how this deals with reading and writing from a register. This confused me for awhile, but I think it makes perfect sense to me now.
So what you said about contamination delay and hold time is correct. This problem applies to when flip-flops are daisy chained. And if you think about it, it also only applies to when you want to read and write at the same time.
Imagine a circuit with just 2 flip flops. It doesn't necessarily have to be a register, just that the first flip-flop is the storage element that is written to, and the 2nd flip-flop is the storage element that reads the first one. If you only needed to read and write on different clock cycles, then none of this delay stuff would matter, because reading would always occur on a different clock cycle when the output of the first was stable, and couldn't change since writing can't occur in the same clock cycle.
However if you wanted to write a new value to the 1st flip-flop, as well as read the previous value properly into the 2nd on the same clock cycle, then that is the exact situation you described, where if the contamination delay of the first was less than the hold time of the second, then writing to the first would thereby contaminate the reading of the second. It makes perfect sense. The read has to occur successfully before the write begins to change what's being read, or else the value gets lost.
Best Answer
The ambiguity comes from the fact that the meeting the hold time requirement depends on the propagation delay.
If you assume that the propagation delay of the FF is always longer than the hold time, then the propagation delay assures that the hold time is met and tclock >= tprop + tsetup.
It would be unusual for the propagation delay of a FF to be shorter than the hold time.
There is of course extra complication caused by the fact that propagation delay, setup, and hold change with voltage and temperature, and you need to account for skew between the clocks at the source and destination FFs.