Electronic – Minimum Clock Period from setup and hold time


I found several different answers to how setup and hold-time of Flip-Flops influence the minimum time between two rising clock edges.

  1. tclock >= Propagation delay + tsetup + thold
  2. tclock >= Propagation delay + tsetup
  3. tclock >= Propagation delay + Max(tsetup, thold)

Which one of them is right?
From my understanding, it should be the first version, but I've found some answers that say that hold-time doesn't change the clock speed.

Best Answer

The ambiguity comes from the fact that the meeting the hold time requirement depends on the propagation delay.

If you assume that the propagation delay of the FF is always longer than the hold time, then the propagation delay assures that the hold time is met and tclock >= tprop + tsetup.

It would be unusual for the propagation delay of a FF to be shorter than the hold time.

There is of course extra complication caused by the fact that propagation delay, setup, and hold change with voltage and temperature, and you need to account for skew between the clocks at the source and destination FFs.