Electronic – MIPS Pipeline Forwarding to MEM

microprocessormips

Consider the following (incomplete) instruction schedule for a MIPS pipeline where loads and stores take three cycles:

               0 1 2 3 4 5 6
...
ADDI R1,R1,#1  F D E M W
SUB R4,R3,R2     F D E M W
SW  R1,0(R3)       F D E M W
...

This is part of a solution to homework problem where we were told that there is only forwarding hardware for ex->ex and mem->ex.

My question is: how does the SW get the correct value for R1? It clearly depends upon the result of the ADDI. But when SW attempts to read R1 from the register file, ADDI has not yet written the result to the register file.

I think this is a fundamental misunderstanding of mine in regards to pipeline registers and forwarding. My guess is that the ADDI could forward the value of R1 via mem->ex forwarding to SW, and it would "hang around", being pushed forward through the pipeline registers until it is needed in the mem stage. But every description I have seen of forwarding to the ex stage involves pushing the result into the ALU, which would be useless here.

Best Answer

Remember that the result of ADDI is known by the end of cycle 2 -- specifically our new value for R1 is going to be available:

  • at cycle 3 (M stage) in E/M, and
  • at cycle 4 (W stage) in M/W

(where E/M and M/W are pipeline registers).

It is available at both these places because we must continue to carry it along until we reach the write-back stage.

Then, looking at just an SW instruction by itself, there are two places we could forward the word data in time for SW:

  • at cycle 4 (E stage) superseding the value of R1 that was in D/E
  • at cycle 5 (M stage) superseding the value of R1 that was in E/M

Your problem constraints permit for M->E forwarding and E->E forwarding. M->E works out here when you look at cycle 4. This is because cycle 4 is not too late to forward for the SW, and our R1 value is available at that moment from register M/W.

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