I have written a verilog code and RTL simulation is working fine. After this I synthesized the design using XST tool in Xilinx ISE 13.2. The post-synthesis simulation is showing some unexpected results. I don't know what went wrong as there were no warnings during simulation. What should I do now? Is there any way to debug post synthesis level netlist? How can I know what my synthesis tool (XST) is doing with my design?
I have included part of my source code. It is for control FSM of my design.
always @ (posedge clock)
begin
case (state) // s0, s1, s2, s3, s_reset are parameters
s_reset:
begin
if(start_proc)
state <= s0;
else
state <= s_reset;
end
s0: begin
pixel_value <= dataOut_bigimage;
pixel_ref <= dataOut_smallimage;
j <= j+1;
if(j==1'b1)
i <= i+1;
if ({i,j} == 2'b11)
if(base_col == 3'b101)
begin
base_row_prev <= base_row;
base_col_prev <= base_col;
base_col <= 3'b000;
base_row <= base_row+1;
end
else
begin
base_col <= base_col+1;
base_col_prev <= base_col;
base_row_prev <= base_row;
end
state <= s1;
end
s1: begin
if (pixel_value <= pixel_ref)
accumulator <= accumulator+1;
else
accumulator <= accumulator;
if({i,j} == 2'b00)
state <= s2;
else state <= s0;
end
s2: begin
if (accumulator > 2'b01)
begin
matchcount <= matchcount+1;
rowmatch[matchcount] <= base_row_prev;
colmatch[matchcount] <= base_col_prev;
end
accumulator <= 2'b00;
if (base_row == 2'b11)
state <= s3;
else
state <= s0;
end
s3: begin
task_done <= 1'b1;
state <= s3;
end
Every thing inside the always block is of reg data type and is properly initialized in a separate initial block
Thanks in advance
Best Answer
Add (and use) a reset signal.
Xilinx FPGAs have a global set/reset (GSR) signal that puts all registers in the their default state or as specified in the register declaration (this is documented in the XST User's Guide at the beginning of chapter 5). AFAIK, the @initial block is ignored.
However, things are chaotic when the FPGA starts up, because:
So the initial Flip-Flop values after the GSR are not enough.
Create a module that generates a reset signal for each clock domain. You can create it by by AND'ing relevant asynchronous reset signals, such as an external reset pin, PLL/DCM locked signals, and using it with a synchronizer, as follows:
(Source: How do I reset my FPGA?)