Electronic – Moore “01010” sequence detector

karnaugh mapsequence-detectorstate-machines

My task is to design Moore sequence detector. As my teacher said, my graph is okay.

I wrote down next states, and outputs, then decided which flip-flops I'll use. With Karnaugh tables, I miminalized functions for them. My problem is, it's not working correctly. When I'm simulating it in Xilinx, after my desired sequence "01010" on the input, I don't get logical 1 on the output. My question is: are my K-tables and way of thinking correct? I can also include my schematic in Xilinx and outcome if needed.

edit: my scheme:
scheme

and the outcome:
simulation

VHDL code:

clock <= '1', '0' after 20 ns, '1' after 40 ns, '0' after 60 ns, '1' after 80 ns, '0' after 100 ns, '1' after 120 ns, '0' after 140 ns, '1' after 160 ns, '0' after 180 ns, '1' after 200 ns,'0' after 220 ns, '1' after 240 ns, '0' after 260 ns, '1' after 280 ns, '0' after 300 ns, '1' after 320 ns, '0' after 340 ns, '1' after 360 ns, '0' after 380 ns, '1' after 400 ns, '0' after 420 ns, '1' after 440 ns, '0' after 460 ns, '1' after 480 ns, '0' after 500 ns, '1' after 520 ns, '0' after 540 ns, '1' after 560 ns, '0' after 580 ns, '1' after 600 ns;
xinput <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns, '0' after 400 ns, '1' after 500 ns;

Updated simulation:

Best Answer

As user W5VO♦ said, it was a matter of changing data on a positive edge. The solution was simple, all I had to do was to move slightly my input signal, so it would be registered on the next rising edge (poor explanation, but I hope everyone knows what I mean). Final outcome looks like this:

Related Solutions

Electronic – sequence detector in verilog

Your regs are defined wrong.

reg presentState ;
reg nextState ;

should be

reg [1:0] presentState ;
reg [1:0] nextState ;

.

By default, regs only have 1 bit so only states a and b can ever be reached.

Also, you should do your testbench a bit differently. Try

initial
begin
@(posedge clk);
@(posedge clk);     sequence <= 1'b1 ; 
@(posedge clk);     sequence <= 1'b0 ; 
@(posedge clk);     sequence <= 1'b0 ; 
@(posedge clk);     sequence <= 1'b1 ; 
@(posedge clk);     sequence <= 1'b1 ; 
@(posedge clk);     sequence <= 1'b0 ; 
@(posedge clk);     sequence <= 1'b1 ; 
@(posedge clk);     sequence <= 1'b0 ; 
@(posedge clk);     sequence <= 1'b1 ; 

$finish;

end

instead.

With those couple of changes, I am getting a pulse on the 'tick' output when I run this in Icarus Verilog.

How to implement sequence detector (multiple sequence)

Recognizing a sequence of symbols is known as "lexical analysis", or more colloquially, "scanning" or "lexing". It's actually a huge topic in software, where an input grammar needs to be broken into meaningful tokens as efficiently as possible. There's a whole process that involves writing a formal grammar for the sequences to be recognized, converting that grammar first to a NFA (nondeterministic finite automaton) and then to a DFA (deterministic finite automaton). The DFA can be described by a table of state transitions that drives a relatively simple and efficient interpreter.

Your problem is a vastly simplified version of that — only two symbols and just two fixed sequences that need to be recognized. It should be solvable pretty much by inspection, without requiring all of the formalism described above.

Just start drawing state diagrams for recognizers for the sequences individually, then look for common sub-sequences and valid end states as you try to combine them into one master state machine.

Here's the diagram that I came up with:

state diagram

The states across the top are the recognizer for "0010", with the final transition that has the output "1" going down to the "10" state, since the last part of this pattern corresponds to the first part of the "100" pattern. Similarly, the states across the bottom are the recognizer for "100", with the final transition going to the "00" state in the top row.

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