This is a simplified view to the problem:
In normal operation (Vin is positive, and Vout has reached its target value), the (high) current flows through the channels of Q2 and Q1. No current flows through the body diode of Q2, in normal operation (it does flow, during startup, as The Photon says). The reason to have two MOSFETs (instead of one MOSFET (Q1) and one Schottky diode (in place of Q2)) is exactly this one. To avoid the voltage drop that otherwise we would have across that Schottky diode.
Why does the current flow through both channels, in normal operation? Because both are on. The LT4356 uses an internal charge pump to generate a voltage Vg higher than Vgs_th for those MOSFETs (which is 2.5 V max). Imagine Vg is around 10 V (actually, between 4.5 V and 14 V). Vg1 is 10 V above Vout. So, Vgs(Q1)=10 V > 2.5 V=Vgs_th, and Q1 is on.
Q3 is on only for negative voltages below -1.4 V. So, in normal operation, Q3 is off. No current flows through the 1 Mohm resistor, and Q2 sees exactly the same Vg as Q1. So, Vg1=Vg2. How about Vgs for Q2? How much is it? Well, if Vout is (for instance) designed to be +12 V, and Vg is 10 V above it, then Vg1=Vg2=22 V. Q2 is on if its Vgs is higher than 2.5 V. For Q2 not to be on, Vin should be higher than Vg2-Vgs_th=22-2.5=19.5 V (!), which will never happen, in normal conditions. In normal conditions, Vin will be only slightly above Vout. So, Q2 is on in normal operation, and its body diode is just short circuited, contributing to zero voltage drop (which was the reason to put there a second MOSFET).
When Vin is reversed, and below -1.4 V, Q3 is on, that makes Vgs(Q2)=0, and there is no way that Q2 may conduct. Also, its body diode will be reversed biased, so it won't conduct, either. Since Q2 is in series with Q1, it does not matter what Q1 does, because no current will flow through any of them, and the load will be safe.
More: the reason for this complexity is that a silicon MOSFET is a device that can carry current in both directions, but can block only in one direction (due to the unavoidable body diode). If that body diode wasn't there, a MOSFET would be an ideal switch (able to carry and block in both directions), and a single MOSFET would be enough. Given that the diode is there, the only way to build a bidirectional-carrying bidirectional-blocking switch with them is by placing two of them in anti-series. With their gates tied together and also either a) (ideally) their sources tied together, or b) their drains tied together (as is the case, here).
GaAs MOSFETs don't have the body diode, and therefore a single device works as an ideal switch.
The use of a MOSFET for reverse voltage protection is very straight forward.
Some of your references are correct but of low relevance and are tending to make the problem look more complex than it is. The key requirements (which you have essentially already identified) are
MOSFET must have enough Vds_max rating for maximum voltage applied
MOSFET Ids_max rating more than ample
Rdson as low as sensibly possible.
Vgs_max not exceeded in final circuit.
Power dissipation as installed able to sensibly handle operating power of I_operating^2 x Rdson_actual
Power dissipation as installed able to handle turn on and off higher dissipation regions.
Gate driven to cutoff "rapidly enough" in real world circuit.
(Worst case - apply Vin correctly and then reverse Vin instantaneously. Is cutoff quick enough?)
In practice this is easily achieved in most cases.
Vin has little effect on operating dissipation.
Rdson needs to be rated for worst case liable to be experienced in practice. About 2 x headlined Rdson is usually safe OR examine data sheets carefully. Use worst case ratings - DO NOT use typical ratings.
Turn on may be slow if desired but note that dissipation needs to be allowed for.
Turn off under reverse polarity must be rapid to allow for sudden application of protection.
What is Iin max ?
You don't say what I_in_max is and this makes quite a difference in practice.
You cited:
"If the drain-to-source voltage is zero, the drain current also becomes zero regardless of gate–to-source voltage. This region is at the left side of the VGS– VGS(th)= VDS boundary line (VGS – VGS(th) > VDS > 0).
and
Even if the drain current is very large, in this region the power dissipation is maintained by minimizing VDS(on)."
Note that these are relatively independent thoughts by the writer. The first is essentially irrelevant to this application.
The second simply says that a low Rdson FET is a good idea.
You said:
Does this configuration fall under the VDS = 0 classification? That seems like a somewhat dangerous assumption to make in a noisy environment (this will be operating in the vicinity of various types of motors), as any voltage offsets between input supply ground and local ground could cause current to flow. Even with that possibility, I'm not sure I need to spec for my maximum load current on the drain current ID. It would then follow that I don't need to dissipate very much power either. I suppose I could mitigate the problem by Zener clamping VGS closer to VGS(th) to reduce drain current/voltage?
Too much thinking :-).
When Vin is OK get FET turned on asap.
Now Vds is as low as it is going to get and is set by Ids^2 x Rdson
Ids = your circuit current.
At 25C ambient Rds will start at value cited at 25C in spec sheet and will rise if/as FET heats. In most cases FET will not heat vastly.
eg 1 20 milliOhm FET at 1 amp gives 20 mW heating. Temperature rise is very low in any sensible pkg with minimal heatsinking. At 10A the dissipation = 10^2 x 0.020 = 2 Watts. This will need a DPAk or TO220 or SOT89 or better pkg and sensible heatsinking. Die temperature may be in 50-100C range and Rdson will increase over nominal 25C value. Worst case you may get say 40 milliOhm and 4 Watts. That is still easy enough to design for.
Added: Using the 6A max you subsequently provided.
PFet = I^2.R. R = P/i^2.
For 1 Watt disspation max you want Rdson = P/i^2 = 1/36 ~= 25 milliohm.
Very easily achieved.
At 10 milliohm P = I^2.R = 36 x 0.01 = 0.36W.
At 360 mW a TO220 will be warm but not hot with no heatsink but good airflow. A trace of flag heatsink will keep it happy.
The following are all under $1.40/1 & in stock at Digikey.
LFPACK 60V 90A 6.4 milliohm !!!!!!!!!!!
TO252 70V 90A 8 milliohm
TO220 60V 50A 8.1 milliohm
You said:
I suppose I could mitigate the problem by Zener clamping VGS closer to VGS(th) to reduce drain current/voltage?
No!
Best saved for last :-).
This is the exact opposite of what is required.
Your protector needs to have minimal impact on the controlled circuit.
The above has mjaximum impact and increases dissipation in protector over what can be achieved by using a sensibly low Rdson FET and turning it on hard.
Best Answer
If you suddenly connect +12 to the input, the source will immediately rise to +11.3 or so because of the body diode conducting.
The gate will charge towards -11.3V with respect to the source through R?. When the gate reaches the threshold voltage the MOSFET channel will begin to conduct, and by the time the gate-source voltage reaches a few volts the MOSFET channel will be conducting almost all the current, the output voltage will be close to +12V. It continues to charge until it reaches about -7.5V at which point the Zener diode begins to shunt significant current away from the gate.
In steady state with 12V in the gate sits at -7.5V with respect to the source, and the MOSFET happily conducts in the reverse direction to normal.
Edit: Regarding the Zener gate protection I would like to graft a comment below into this answer