Generally-speaking, larger capacitor packages increase the current loop through the part, so the inductance (ESL) is greater. Similarly, the extra material means the resistance (ESR) is higher. When you put the ESL and capacitance together for decoupling applications, you get an LC tank circuit with a resonant frequency that decreases with increasing inductance and capacitance. The ESR in this circuit represents the minimum impedance at resonance.
When decoupling, you normally want to get below a certain impedance over the operating frequency range of the device in question. To achieve this you need multiple LC circuits covering different parts of that frequency spectrum. This is why you need a range of different capacitor sizes.
In order to achieve your desired ESR, you may also need several capacitors in parallel rather than one, as the ESR goes in parallel as well and will therefore be lower.
As a last note, also bear in mind that the escape pattern you use (position and number of vias & traces) from decoupling caps can dramatically affect the decoupling performance as well, because they add to the inductance. When you get below 0201 caps you can find that the overall inductance actually increases with smaller cap size because of this.
Power supplies take time to respond to a demand for more current from the device. The capacitors act as a local reserve until the power supply responds.
Digital logic devices demand current very abruptly (due to the steep logic edges). The inductance of the power supply traces makes it impossible to transfer a step in current from a power supply to the logic chip. To solve the problem, one places "decoupling" capacitors very close to the chip. As the remaining traces are very short, the edge problem is reduced.
The reason for the two different types of capacitors is as follows:
The device apparently requires a 10µF decoupling capacitor. Capacitors of this size are typically electrolytic capacitors. The problem is: they respond quite slowly compared to the edge time.
To solve the problem, one places a (typically) ceramic capacitor in parallel. To simplify the issue: they only exist in fairly small values.
Functioning: The ceramic capacitor (100nF) smoothes the edge time of any current requests from the device and the electrolytic capacitor (10µF) supplies the bulk of the current once it kicks in.