We are designing PCB with multiple ICs (up to 10 ICs). Each IC has MDIO and JTAG interface. The board has two signal layers, one power layer and GND plane. We have to route JTAG and MDIO lines to each IC, so the tracks become pretty long and what is the main point of concern – there are too many vias between layers.
For example while I was routing JTAG TCK track to the last IC, I had to add 8 vias. As far us I understand each via adds some inductance to the line, so the high frequency components of the clock may be attenuated. Should we consider for the number of vias and trace length while routing JTAG and MDIO pins? And also how the number of vias influences the wave impedance?
Is it a good practice to route high speed nets like 100BASE-TX diff pairs using some vias? Or we must add extra layers to keep the number of through hole vias less than two?
Best Answer
If your concern that adding via adds inductance to the line, don't forget the trace itself is an inductor, and capacitor.
Via wouldn't significantly increase your trace inductance if this one is already long.
How "long" is long ? I've got designs with JTAG over pretty long traces, like 10cm. And even the JTAG often have some extra wires from the connector.
You can increase the trace width in order to reduce the resistance and that will reduce the negative effect of the inductance (It won't reduce the inductance, but the "resistance" of the line that is in serie with the inductance).
For high speed, via won't be too much of a concern, it is even sometimes necessary especially if you have through hole connectors, you have to avoid rigging down the pin of the connector and you need to route from the bottom of the pcb, like in USB-C.