Electronic – Multiplication in VHDL

vhdlxilinx

I am trying to make a simple MACC to work, but it does unexpected things.
The multiplication is not working. 00001 * 00001 outputs 00000

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity macc is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           en : in  STD_LOGIC;
           A : in  STD_LOGIC_VECTOR (4 downto 0);
           B : in  STD_LOGIC_VECTOR (4 downto 0);
           P : out  STD_LOGIC_VECTOR (8 downto 0));
end macc;

architecture Behavioral of macc is
    signal product : STD_LOGIC_VECTOR (8 downto 0);
    signal acc_in : STD_LOGIC_VECTOR (8 downto 0);
    signal acc_out : STD_LOGIC_VECTOR (8 downto 0);
begin

    product <= A*B;
    acc_in <= acc_out + product;

        acc: process is
        begin
        wait until rising_edge(clk);
            if (rst = '1') then
                    acc_out <= (others => '0');     
            elsif (en = '1') then
                    acc_out <=  acc_in;
            end if;
        end process acc;

    P <= acc_out;

end Behavioral;

Multiplication mistake

Best Answer

If you multiply 2 5-bit numbers (A and B are both std_logic_vector(4 downto 0)) don't you need 10 bits (not 9) to store it in (so P should be std_logic_vector(9 downto 0)? (31*31 = 961: needs 10 bits)

But also - don't use std_logic_arith/_unsigned. Use ieee.numeric_std and then use the unsigned data type.

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