I am adding two hex numbers and determining what bits in the condition code register.
The numbers I am adding are 4D (base 16) and 66 (base 16). I converted both to their binary equivalents.
4D (base 16) = 0 1 0 0 1 1 0 1
66 (base 16) = 0 1 1 0 0 1 1 0
Once I added these I got 1 0 1 1 0 0 1 1. By looking at the MSB (bit 7), it is 1 which makes the number negative and the N bit is set to one. I was looking at my notes, when a number is negative, it is represented by its 2s complement.
so:
1 0 1 1 0 0 1 1 = -(0 1 0 0 1 1 0 0 + 1) = - 0 1 0 0 1 1 0 1 = -4D (base 16) = -77 (base 10).
My professor said the V bit is set to 1 because of 2s complement overflow. For the 8 bit processor, the maximum value is +127 (base 10) and the minimum value is -128 (base 10). I thought 2s complement overflow occurred when the answer is outside these bounds. My answer is within these bounds so 2s complement overflow does not occur so I was wondering why the V bit is set to 1.
I put this into a hexadecimal calculator and it says the answer is B3 (base 16) which is what I got by just adding the numbers. This converts to 179 (base 10) which does go outside the bounds and the V bit would be set to 1.
So my professor did an extra step after I added the two numbers to display the negative equivalent. When should I determine if the V bit should be set, and what should the actual answer be, B3 or -4D?
Best Answer
A 2's complement overflow is indicated when the source values have the same sign but the resultant sign differs. In the case of your example, both source values have 0 as the MSB but the result has 1, therefore an overflow has occurred.
The sum is 0xB3, since the result itself is not modified by the status registers, only how you treat it after the fact.