Electronic – Numeric literal constant in VHDL treatment

Integers are fine in synthesis, I use them all the time.

I use std_logic at top level ports, but internally I was using ranged integers all over the place

That's fine!

Be aware:

• You are simulating first aren't you :) - Integer types don't automatically "roll-over" in simulation - it's an error to go out of the range you've specified for them. If you want roll-over behaviour, you have to code it explicitly.
• They are only specced to go from \$-(2^{31}-1)\$ to \$+2^{31}-1\$ (i.e. not quite the full range of a 32-bit integer, you can't use \$-2^{31}\$ and remain portable), which is a bit of a pain at times. If you need to use "big" numbers, you'll have to use unsigned and signed.
• If you don't constrain them, you can sometimes end up with 32-bit counters where less would do (if the synth and subsequent tools can't "see" that they could optimise bits away).

On the upside:

• They are much faster to simulate than unsigned/signed vectors
• They don't automatically roll-over in simulation (yes, it's in both lists :). This is handy - for example you get early warning that your counter is too small.

When you do use vector types, you are using ieee.numeric_std, not ieee.std_logic_arith aren't you?

I use integers where I can, but if I explicitly want "roll-over n-bit counters", I tend to use unsigned.

The reason your unsigned() cast doesn't work is because the result takes the exact bits in the input and just 'calls it unsigned'. ie, 0xFFFC signed is -4, but when cast to unsigned, it's 65532.

Instead, since your incoming signal is always 16 bit signed, just check to see if it is negative (as simple as checking the leading bit). Then, instead of casting to unsigned, negate it (which will have the desired effect) and then multiply by your scale factor, negating again afterwards. I can't think at the moment how to do this in a single step, but this should work for you if you can spare two extra multiplies.