Electronic – Odd PCB Layout for Voltage Regulator

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I am reverse-engineering a board which has a Xilinx Spartan 3E FPGA, with VCCAUX powered by a 2.5 volt regulator. Below is the PCB layout for the regulator part of the circuit, and something seems very fishy to me.

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My apologies for the horrible pixelation, this was the highest resolution I could get with the equipment I had available. Anyway, the SOT23-5 component labeled "LFSB" is a Texas Instruments LP3988IMF-2.5 linear voltage regulator. I have traced out the schematic below from the board layout:

enter image description here

You may already have noticed the source of my confusion: I have no idea why they would have placed a 316 ohm resistor directly across the output of a 2.5 volt regulator. All that does is waste 7.9 milliamps. I cannot seem to find any reason for doing this. I wonder if it is a design flaw, and that resistor is actually supposed to be connected to the PG pin instead of to ground. I have triple-checked the original PCB, though, and it definitely connects to ground and the PG pin is not connected to anything. If this is an error, however, it would explain why they used a separate trace on the low side of the resistor instead of connecting it to the copper ground pour that's right there. I also wondered if the regulator may require a minimum load in order to maintain a stable output, but that is not the case for this regulator. There are no minimum load requirements. I also considered the possibility that it was intended to bring up VCCAUX more slowly for sequencing purposes for the FPGA, but reading the datasheet this also does not seem to fit – there are no strict sequencing rules for powering up the Spartan 3E.

Can anyone think of a reason why someone would intentionally place a 316 ohm resistor directly across the output of a 2.5V regulator? I considered it might be a bleeder resistor for the output capacitor, but it seems like too low of a value for that.

EDIT:
Perhaps this additional information will help. The datasheet for the Spartan 3E specifies what the VCCAUX supply is used for:

VCCAUX: Auxiliary supply voltage. Supplies Digital Clock Managers (DCMs), differential drivers, dedicated configuration pins, JTAG interface. Input to Power-On Reset (POR) circuit.

Best Answer

I would have done the same design, in order to reduce dynamic and static load regulation error.

The details for the reasons are evident in the datasheet.

  • look at dynamic load regulation error and input step regulation error.

  • I can only guess what error budget the designer had in mind, but it common for every LDO to have the above responses , although this FET LDO is exceptional low power and dropout voltage.

    • 5mV error {input step=0.6V} with 1mA step load, 200mV error with 150mA step load*
    • the static load regulation error is only rated above 1mA as 0.007%/mA . This implies it is worse below 1 mA and improves with a dummy load of 7.6mA to the designers satisfaction. It also improves dynamic step load regulation error above.*

This 1mA ensures the rise fall time of Gate drive to speed up response. 7.6mA is even better with diminishing returns above this.

  • static load regulation error is only due to RdsOn of the PFET used in the LDO divided by its internal Loop gain. This true for any voltage regulator whether it is FET or BJT. But infinite loop gain can increase stability errors or more ringing, under certain load , (ESR, C ) conditions so it is finite.

Fishy? No way

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