Electronic – One-clock increment operation in a three-bus CPU architecture

buscpudigital-logicregister

In his chapter on CPU design, Edward Bosworth introduces the following three-bus architecture:

three bus CPU

One of the main design aims of this circuit is to be able to increment the program counter PC in a single clock cycle. According the the accompanying text, this is achieved by driving B1 from PC, B2 from the +1 constant register, asserting the add signal on the ALU and driving PC from B3:

PC <- PC+1: PC -> B1, 1 -> B2, add, B3 -> PC

The obvious question is then, how can the PC register drive B1 with one value while simultaneously loading another value from B3?

I can come up with two possible workarounds, but both have obvious issues.

  1. The transfers do not happen simultaneously. For example, B1 is driven on the rising edge, whereas the signal is loaded from B3 on the falling edge. But then, when we stop driving B1 the signal would vanish on B3 in the absence of another register in the path. If you do use an intermediate register somewhere (in the ALU?), you really are just doing two-cycle increment using half-cycle cycles.
  2. The PC register is actually two registers, one for output and one for input, that are not connected when the register is loading. But then you would need some sort of "equalization logic" that could turn out to be non-trivial.

So what is going on here?

Best Answer

Turns out I missed a crucial detail in the accompanying text, and the registers are indeed composed out of two (master-slave) sub-registers:

The Use of Master–Slave Registers

Note that the contents of the PC are incremented within the same clock pulse. As a direct consequence, the PC must be implemented as a master–slave flip–flop; one that responds to its input only during the positive phase of the clock. In the design of this computer, all registers in the CPU will be implemented as master–slave flip–flops.

Related Topic