Electronic – Operational amplifier as a comparator at high frequency

You have two errors which impact your 20 kHz simulation.

The first is your hold capacitor. At 1 uF, a 15 V/usec slew rate requires a charge current $$\frac{dV}{dt} = \frac {i}{C} $$ $$i = C\times \frac{dV}{dt} = 10^{-6}\times 15\times 10^6 = 15 \text{ amps} $$ and there is simply no way you'll get that out of an AD825. A 20kHz, 3.4 volt triangle wave requires $$ \frac{dV}{dt} = 2\times3.4\times2\times 10^4 = 1.3\times 10^5\text V/\mu sec$$ This is about 100 times less than the pulse requirement, but it's still too much for the AD825. If you pay close attention to the output of your simulator, you'll see the reason the output is low is that the output noticeably lags the input, and the hold capacitor stops charging while the voltage is too low.

You can see that the output (red) does not charge fast enough to follow the input (green), and the output levels off when the input drops below the output. In other words, the peak detector is working as well as it can given the slow response at the capacitor.

The answer is simple: reduce your hold capacitor. A 1 nF will work very nicely on your circuit.

Once you do that, you'll see a new problem: droop on the output. This is also pretty simple. When you set up your simulation, you used the default iN1183 diodes, and even by 40 year old standards the 1183 is pretty crappy. Specifically, its reverse bias current is horrible. Replace the diodes with 1N4148s and see how you like that.

Now change your simulation input to a 100 nsec pulse, and be disappointed. The capacitor overcharges and once that happens you have no way to discharge it other than using the FET. Reducing the hold capacitor still further will reduce the problem, but it is an artificial solution, and will not work reliably if the input pulse width or amplitude vary. Your problem is simply that the AD825 is too slow to handle 100 nsec pulses in this configuration. Although the data sheet shows it settling acceptably for amplifying 100 nsec pulses, that is not what you are doing. Between the time delay associated with charging the hold capacitor and the intrinsic delay caused by the second AD825, you simply cannot accurately do what you want with this op amp.

EDIT - Also, just for fun, try changing the hold capacitor to 100 nF, to see that this is not a simple amplifier.

I believe you simply do not have the MAX492 biased correctly. Look at the "Common Mode Input Voltage Range" ("CMIVR") in the MAX492 data sheet. It goes from Vee-0.25 to Vcc+.25. This is the legitimate range of voltage you should be applying to either input on the MAX492.

Since your L-C circuit is grounded to the power supply common, its sinusoidal voltage output will swing above and below ground. On the positive cycle this is OK, but on the negative cycle you are violating the CMIVR of the MAX492 by dipping to far below ground.

You will want to bias the output of the L-C to 1/2 Vcc by make capacitively coupling the L-C output to 2.5 volts and connect this signal to the NI input of the op-amp. This will position the L-C's output squarely in the middle of the legitimate CMIVR.

You can make the 2.5 volt bias point with a simple resistive divider between 5 VDC and GND. The coupling capacitor needs to have a low reactance at the resonant frequency of the L-C. You have to choose the resistor values (both are equal) so they don't swamp out the L-C's output. I'd start with 20KOhms each and compare results with the unloaded output of the L-C. If the loaded output is significantly swamped, go higher on the resistors.