Electronic – Optimizing Simple Logical Design

circuit-design

I have a question about what looks to me like a non-minterm/maxterm minimization of a simple logical circuit. Sidenote: This seemed like the right place to ask this question, but let me know if there's a more appropriate community here on stackflow that specifically handles questions like these.

I noticed that the full adder can be decomposed into the two half adders. The logical circuit for the nth + 1 carry over bit is represented in minterm form as xy + xc + yc where x and y are the two bits being added and c is a carry over bit from a previous addition. This can be rewritten after some algebraic maniplulation as xy + (x Xor y)c. This isn't a simplification but a design choice that makes efficent use of the fact that there already exists an x XOR y implementation elsewhere in the circuit of the full adder, namely for computing the s bit. If the x Xor y element wasn't present, there'd be no logical reason (disregarding other aspects of circuit design) to replace the x or y element in this circuit with the x Xor y element.

In simple cases like these, its easy to spot these sorts of "minimizations". But for larger circuits it become very difficult to do so and since no textbook I've come across talks about this technique, I have a few questions.

  1. What's this kind of optimization called?
  2. Is it commonly used in industry?
  3. If it is, how do engineers using CAD tools tell the computer to look for something like this? I mean, it seems like it would be very computationally intensive.

Thanks in advance!

Best Answer

Edit: So sorry! Turns out I didn't read far enough into my textbook. There was an obscure section right at the end of the chapter that answered my question.

For anyone wondering, the textbook is Fundamentals of Digital Logic with Verilog Design by Brown and Vranesic and the section is 2.15.

Sorry again for the bother!