Electronic – Organization of large memory using memory blocks


I found the following question in a test. I am not looking for an answer to the question per se, but I am having difficulty understanding the part in bold, as explained below.

A main memory unit with a capacity of 4 megabytes is built using 1M×1-bit
DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row.
time taken for a single refresh operation is 100 nanoseconds. The time required
to perform one refresh operation on all the cells in the memory unit is?

As far as I know, an m x n memory chip has m rows of n cells each. Hence, the given chip should have 1M rows of 1 cell each. How come the bigger memory unit built out of it has 1k cells in each row?

What is the mistake I am making here? Is my understanding of the memory chip specification incorrect, or is there a way of reconfiguring memory chips to have more columns per row that I do not understand? Can someone please explain this to me?

Best Answer

From the outside, each memory chip is organized as 1M words of 1 bit each, which means that it takes 20 address bits to specify a word.

Internally, the memory is physically organized as a square matrix of 1024 rows and 1024 columns, with one bit in each position in the matrix.

There are at least two reasons that the physical organization is important to the question:

  1. The memory chip only has 10 address pins. The full 20-bit address is fed into the chip in two stages, the 10-bit row address first, and then the 10-bit column address.

  2. When a refresh operation occurs, an entire row is refreshed all at once.