I'm trying to troubleshoot a piezo-driver circuit, which uses a PA84 op amp (10x gain). The schematic I'm working from indicates the supply voltages should be +200 / -15 V, which are well within spec… however, I'm getting a lot of noise on the output.
For example, looking at just CH2 in the schematic with no input signal, I'm seeing a threshold voltage for the DC bias input, where I move from virtually no noise (~ mV) to a lot of noise (~V) on the output. With the +200/-15 volt supply voltages on my op amp, the threshold is at about -1.5 V after the R45 pot (~30 V at CH2 out). I noticed, though, that reducing the V_s voltages to e.g., +100V / -15 changed this threshold so I could scan the pot R45 across its entire range without moving into a region of instability.
Has anyone encountered a similar issue before, or have any suggestions/pointers? It's not intuitive to me why the supply voltage would have such a noticeable impact on the op amp's stability… although to be fair, i'm very new to all this 😛
NOTE: I also have a 4pf bandwidth-limiting capacitor across the op amp, in parallel with R19,R20,R21. This isn't on the JILA circuit posted online, but was necessary to get rid of serious op-amp oscillations. I've also put in a 10nF capacitor in parallel with R9, which was in a different (paper) copy of the same circuit given to me from someone who used to work at JILA (unclear why there is a discrepancy with the public domain circuit posted on their website…). The paper copy also shows a 3pF (not 4pF) bandwidth-limiting capacitor — I'm using the 4pF one while waiting for the 3pF one to arrive. The circuit is also laid out on a PCB, and so there could be some issues with my design layout there…
Best Answer
If I were to guess, I would say that the circuit is falling victim to its wacky biasing scheme. A valiant attempt is made in the negative reference voltage generation to ensure good power supply rejection, with lots of bypassing (with capacitors of several sizes) and buffering. But this might not compensate for the op-amp being on wildly assymetric power rails. Everything in the datasheet assumes symmetric power rails.
Never mind that. Let's look at something else. In the specifications table in the datasheet we see something interesting under Common Mode Voltage Range. Namely, it can be as bad as plus/minus \$V_s - 10\$! Uh oh! This means that your circuit should ensure that the inputs of the PA84 do not go within 10 volts of either power rail. I suspect that the -VREF line alone could be violating that, even with no signal. Your manipulations of the potentiometer could be taking the device beyond the common mode input range.