Electronic – Paging out ROM after boot up

logic-gatesramrom;

Building a Z80 computer, would like to boot CP/M from ROM and switch the ROM off after initial boot to make whole 64k RAM available for the CPU.

Solution I've got so far is using a flip-flop to disable ROM (and enable RAM) when a specific address range (0x8000-0xBFFF – i.e. A15=1, A14=0) appears on the bus. CP/M code starts from 0xDC00 so no issues with this approach as far as I can see.

Upon a reset, ROM and RAM2 becomes active, and once the switch occurs RAM1 and RAM2 stays active until the next reset.

1 – I tried to go through every case and it seems to be correct, but do you see any issues with this design?

2 – Can you sport any further simplifications? I feel like I used too many NAND gates πŸ™‚

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Note: This is a follow up to a question on RC.SE, as it was mentioned there, that SE.EE would be more relevant. This solution is partly based on recommendations given previously.

EDIT: Revised version to incorporate MREQ:

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Best Answer

The below circuit shows how it can be done. The principle is taken from the Z80 Second Processor for the BBC Micro and I'm sure the idea was around long before then, these things usually are.

The Z80 will use two address maps: a start-up map with the ROM available (ALLRAM is LOW) and the operating map with no ROM, just RAM (ALLRAM is HIGH).

schematic

simulate this circuit – Schematic created using CircuitLab

The start-up address map is:

ADDRESS RANGE    READ                 WRITE
0000..3FFFh      ROM image (16 KB)    RAM Low (first  16 KB)
4000..7FFFh      ROM image (16 KB)    RAM Low (second 16 KB)
8000..FFFFh      RAM High  (32 KB)    RAM High

Note that the ROM image appears twice. This harmlessly simplifies the address decoding. All writes in the 64 KB map go to the 64 KB RAM, so the RAM can be initialised easily.

The operating address map is:

ADDRESS RANGE    READ AND WRITE
0000..3FFFh      RAM Low  (32 KB)
8000..FFFFh      RAM High (32 KB)

The start-up address map is in use until the first instruction fetch from the upper 32 KB, which is always RAM.

After reset, the Z80 will execute from ROM address 0000h. Its ROM software can then follow the following example steps to get into the operating mode and be running CP/M:

Initialise the RAM with CP/M, copied from the ROM or wherever.
Store a 3-byte 'JP startCPM' instruction at 8000..8002h.
Do anything else the ROM needs to, before it vanishes until the next /RESET.
Execute a 'JP 8000h' instruction from ROM.

At the start of the JP instruction byte fetch cycle from 8000h, the D-type Flip-Flop (DFF) output ALLRAM will be preset to HIGH. ALLRAM will stay HIGH until the next /RESET.

This circuit uses OR and NOR logic gates, to illustrate the mechanisms used. It may well be possible to optimise it into fewer gates. When building one for real, though, you could look at using a CPLD instead (5 V-tolerant or 3V3, depending on your Z80 and memories) such as an XC9500XL part. A CPLD would be cheap and mop up the gates but it just depends what suits you.