# Electronic – Paralleling Mosfets: Can I use a common gate resistor, or do I have to use a separate one for each mosfet

gate-drivingmosfet

When calculating gate resistor for a single mosfet, first I model the circuit as a series RLC circuit. Where, `R` is the gate resistor to be calculated. `L` is the trace inductance between the mosfet gate and the output of the mosfet driver. `C` is the input capacitance seen from the mosfet gate (given as \\$C_{iss}\\$ in mosfet data sheet). Then I calculate the value of `R` for appropriate damping ratio, rise time and overshoot.

Do these steps change when there are more than one mosfets connected in parallels. Can I simplify the circuit by not using separate gate resistor for each mosfet, or is it recommended to use separate gate resistors for every mosfet? If yes, can I take `C` as the sum of gate capacitors of each mosfet?

simulate this circuit – Schematic created using CircuitLab

In particular, I am aiming to drive a H-bridge made of TK39N60XS1F-ND. Each branch will have two paralleled mosfets (8 mosfets at total). The mosfet driver section will consist of two UCC21225A. The working frequency will be between 50kHz and 100kHz. The load will be primary of a transformer with an inductance of 31.83mH or more.

Depends, And that depends is based upon your REAL circuit not your intended circuit

simulate this circuit – Schematic created using CircuitLab

Your practical placement will create something like this (there will be a few other stray inductances but for now this will do).

If you think about the current flow when you charge/discharge the gates it will be

1. MOSFET driver
2. Gate resistor
3. Split path to the MOSFET
4. via each MOSFET source
5. recombine at the common reference
6. via some path back to the MOSFET driver

This loop is one you need to keep BALANCED & ideally minimised. Imagine if due to poor layout/tracking/wiring the right FET's source had 10x the inductance on the gate and/or source, it will switch slower which mean the left FET will experience more of the transient responses.

In large power devices they use a small individual gate resistor per die & then parallel all the devices up, but they keep the layout really-really tight & equally they are in control of the MOSEFET/IGBT batch characteristics for very closely matched devices . If you cannot do this then it is better to have a separate gate resistor.

Parallel IGBT die on a common substrate

The benefits of a separate gate resistor is, if you need to tune the response of one leg based upon other observations, you can