digital-logictiming-analysis
I have to calculate the clock paths in a circuit and I have a 2 dual positive-edge-triggered D-TYPE FLIP-FLOP with clear and reset called DFF1 and DFF2.
Data sheet: http://www.ti.com/lit/ds/symlink/sn74lvc74a-q1.pdf
what does it mean: the CLR and SET pins of the two flip-flops are set such that {DFF1,DFF2} are reset to {1,0}?
Thanks!
The basic difference is a gating or clocking mechanism. For example, let us talk about SR latch and SR flip-flops.
An SR Latch will look like this
In this circuit when you Set S as active the output Q would be high and Q' will be low. This is irrespective of anything else. (This is an active low circuit so active here means low, but for an active high circuit active would mean high)
An SR Flip-Flop (also called gated or clocked SR latch) looks like this.
In this circuit the output is changed (i.e. the stored data is changed) only when you give a active clock signal. Otherwise, even if the S or R is active the data will not change. This mechanism is used to synchronize circuits and registers so that the data does not change unnecessarily.
You mention that the table looks like a T flip flop. Is it possible you are interpreting the table incorrectly?
I believe the "QN" column represents "Q NOT", where the "Q" column is the value of Q resulting from the specific input. In this case, the table correctly represents the behavior of a D flip flop.
Best Answer
I don't see the sentence you provide in the datasheet. Instead the datasheet says:
A PRE input sets the Q to 1, a CLR input sets the Q to 0. There are two flip-flops in this chip, so PRE1 and CLR1 are for the first flip-flop while PRE2 and CLR2 are for the second flip-flop.