in my experience having truly separate AGND and DGND nets almost never works out well in practice. 90% of the designs i see that try to do this end up with current loops that introduce EMI issues and can generate more noise in the analog portions of the circuit than using a single ground with careful part placement would.
Having two GND planes also creates a problem for routing in that signals referenced to a particular ground should only ever be run on layers that are adjacent to this plane or its associate power plane. This can result is a pretty funky stack up that can limit where you can run traces. Your best answer would be AGND,signal,?GND,POWER,signal,DGND but thats funky to layout, uses lots of vias, only gives 2 signal layers to route on.
What i would recommend is a single solid ground plane and careful part placement. High speed digital signals and noise will follow the path of least inductance to ground not the path of least resistance. The path of least inductance is the smallest loop area, for signals this is directly under the trace on the adjacent ground plane. In some cases a ground pour on top, bottom, or both can be helpful in reducing noise pick up as well. This is dependent on the components and the design layout.
Create virtual partitions, keep out areas, where you only run either analog or digital signals, keeping in mind that the return current path for the low frequency analog signals is the path of least resistance, while the return path for the high speed digital signals is the path of least inductance. As long as your careful to ensure that the return current paths don't cross, especially a digital return running under your analog sections. You shouldn't get much noise pick up at all.
If your have a particular device that is very sensitive to noise, such as a high resolution ADC, you can use a ground island to increase noise immunity, like this:
alt text http://www.hottconsultants.com/techtips/a-d%20gnd%20plane.gif
In cases where i have some sensitive analog circuitry i will usually also use a power island that is separated from the digital power supply by an LC filter of some sort, depending on the digital frequencies i'm wishing to block.
This is a difficult problem to cover in a couple of hundred words, so this will be brief and you'll just have to do some research on your own. But I'll try to summarize it enough so you at least know what to research.
You need to know about trace impedance, signal termination, signal return paths, and bypass/decoupling caps. If you got these absolutely correct then you would have zero EMC problems. Getting it 100% perfect is impossible, but you can get much closer than you are now.
First, let's look at signal return paths... For every signal there must be a return path. Normally the return is on the power or ground plane, but it could be somewhere else too. On your PCB, the return is on a plane. The return path goes from the receiver back to the driver. The loop area is the physical loop created by the signal plus the return path. Normally the laws of physics will cause the loop area to be as small as possible-- but PCB routing wants to mess that up.
The larger the loop area, the more RF problems you will have. Not only will you emit more RF than you want, but you will also receive more RF.
The signals on the bottom (blue) layer will want their return path to be on the adjacent plane on the next layer (cyan)-- since that makes the loop area as small as possible. Signals on the top (red) layer will have their return path on the gold layer.
If a signal starts on the top layer then goes through a via to the bottom layer then the signal return path will want to switch from the gold to cyan layers, at the point of the via! This is a major function of decoupling caps. Normally one plane would be GND and the other would be VCC. A signal return path can go through the decoupling cap when switching between planes. That is why it is often important to have caps between planes even when it is not obviously needed for power reasons.
Without a decoupling cap between planes, the return path cannot take a more direct route and so the loop area increases in size-- and EMC problems increase.
But voids/splits in the planes can be even more problematic. Your gold layer has split planes, and signal traces, which create problems. If you compare the red and gold layers you will see how signals cross the voids in the planes. Every time a signal crosses a void in the plane then something is going to go bad. The return current is going to be on the plane, but it can't follow the trace across the void so it has to take a major detour. This increases loop area and your EMC problems.
You can place a cap across the void, right where the signals cross. But a better approach would be to reroute things to avoid this in the first place.
Another way the same problem can be created is when you have several vias that are close together. The clearance between the vias and the plane can create slots in the planes. Either decrease the clearance, or spread the vias out so a slot does not form.
Ok, so that's the biggest issue with your board. Once you understand that then you have to look at signal termination and controlling trace impedance. After that, you have to look at shielding and chassis GND issues with your Ethernet connection (not enough info in the Q to comment accurately).
I hope that helps. I really breezed by the issues but that should get you going.
Best Answer
As said by others, the color is the result of the solder mask used.
However, it's definitely not true that color is the only difference. For example, Paul Stoffregen of Teensy fame found that a black solder mask had reduced resolution than a green solder mask, and this directly led to lower reliability of black boards.