I typically use 2 ounce copper as rule for all my PCBs. On a recent board I am using a 0.5mm pitch, relatively large micro, and noticed the pads aren't very flat. Assembly went fine with the protos, but I'm wondering if 1 once copper would provide for a flatter landing service. Does anyone have any experience with using 1 and 2 ounce copper with small pitch devices and/or any advice on assembly reliability related to copper thickness for such devices?
Electronic – PCB copper thickness with small pitch SMT components
pcbpcb-assemblysurface-mount
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I'm late to the game, but I'll give it a shot:
1- It appears that for a lot of manufacturing houses, 105 microns is as high as its gets. Is that correct or are higher thickness possible?
Some fab shops can plate up internal layers. The tradeoff is usually larger tolerance in the overall thickness of the board, e.g. 20% instead of 10%, higher cost, and later ship dates.
2- Can the copper in the inner layers be as thick as the copper at the top and bottom of the board?
Yes, though inner layers do not dissipate heat as well as outer layers, and if you're using impedance control, they are more likely to be striplines than microstrips (i.e. using two reference planes instead of one). Striplines are harder to get a target impedance; microstrips on the outer layers can just be plated up until impedance is close enough, but you can't do that with internal layers after the layers are laminated together.
3- If I'm pushing current through several board layers, is it necessary or preferred (or even possible?) to distribute the current as equally as possible throughout the layers?
Yes, it is preferred, but it is also difficult. Usually this is only done with the ground planes, by way of stitching vias and mandating that holes and vias connect to all planes of the same net.
4- About the IPC rules regarding trace widths: Do they hold up in real life? For 30 Amps and a 10 degrees temperature rise, if I'm reading the graphs correctly, I need about 11mms of trace width on the top or bottom layer.
The new IPC standard on current capacity (IPC-2152) holds up well in real life. However, never forget that the standard does not account for nearby traces also generating comparable amounts of heat. Finally, be sure to check voltage drops on your traces as well to make sure they are acceptable.
Also, the standard does not account for increased resistance due to skin effect for high-frequency (e.g. switching power loop) circuits. Skin depth for 1 MHz is about the thickness of 2 oz. (70 µm) copper. 10 MHz is less than 1/2 oz. copper. Both sides of the copper are only used if return currents are flowing in parallel layers on both sides of the layer in question, which is usually not the case. In other words, current prefers the side facing the path of the corresponding return current (usually a ground plane).
5- When connecting multiple layers of high current traces, what's the better practice: Placing an array or grid of vias close to the current source, or placing the vias throughout the high current trace?
It's best (and usually easier from a practical point of view) to spread the stitching vias out. Also, there is an important thing to keep in mind: mutual inductance. If you place vias that carry current flowing in the same direction too close to each other, there will be mutual inductance between them, increasing the total inductance of the vias (possibly making a 4x4 grid of vias look like a 2x2 or 1x2 at decoupling capacitor frequencies). The rule of thumb is to keep these vias at least one board thickness from each other (easier) or at least twice the distance between the planes the vias are connecting (more math).
Finally, it is still wise to keep the board's layer stackup symmetric to prevent board warpage. Some fab shops may be willing to go to the extra effort to fight the warpage from an asymmetric stackup, usually by increasing lead times and cost since they have to take a couple tries at it to get it right for your stackup.
Increasing the plating thickness of copper does increase its ability to remove heat. Increasing the number of copper planes also works, as long as they are stitched together by an adequate number of via holes, whose copper sides will conduct heat between the planes.
As George pointed out, extra copper area also improves heatsinking. To get the full benefit of copper plane heatsinking, you need both area and thickness. A small thick area round your device isn't able to lose much heat, although it conducts it well. A large thin area isn't able to pull much heat out of the device, although it can lose it well. You need both thickness, and potentially multiple planes around the device to minimise the temperature drop to the rest of the heatsink, then a large area to lose the heat without too much temperature rise above ambient.
If you are to do any serious board designing for heat, then you need a thermometer, and to measure the temperature of different parts of your prototype when it's dissipating power. If your copper plane is hot, it needs more area, or better connection to chassis or heatsink to lose the heat. If your copper plane is cool and your device hot, then you need more copper thickness around the device.
With enough via holes, the heatsink can be placed on the bottom of the board, and remove heat from the component on the top side. A fully filled via, whether fully plated, or solder-filled, conducts heat better than a typical tubular via.
Be warned though that increasing the amount of copper round and/or under a part's footprint makes rework increasingly difficult, or increasingly reliant on devices with better control and more heat delivery capacity than a simple soldering iron.
Best Answer
Unless you need high-current capability, 1 oz is the default thisckness. Line definition can be impaired with increased thickness, so only use when necessary.