Electronic – PCB layout questions for MCU breakout board


I'm attempting to route a board that is, essentially, a breakout for the LPC23xx/LPC17xx MCU. I've never routed anything approaching this complexity before, and I have a few areas of concern. I know that a four-layer PCB would be optimal, but I'm a hobbyist, and turning this into a four-layer board would make this as expensive as commercially-available options. I've based my design on a couple of proven two-layer commercial boards, so I know that it is possible to make this work. First, this is the mostly-routed board (ignore all the USB machinery on the right, I haven't even decided for sure whether to include it) (also, I know the silkscreen is horrid, I haven't worked that out yet):

LPC23xx/LPC17xx breakout board

1) One area of concern I have is the length of traces between the MCU and crystals (one is for the RTC, the other is for the MCU). They're no longer than either of the boards that I based my design on, but I would like a bit of validation.

crystal traces close-up

2) Another concern I have is decoupling. I know that, in general, there is no such thing as too much decoupling, but in this case, I'm short on space, so I haven't decoupled ALL of the VCC/GND pairs (there's a lot!). Both of the boards I based my design on have only 2 decoupling caps, and I have three, so I may be good there. Should I work to get at least one or two more in?

decoupling capacitors

3) I've worked quite hard to provide a nearly-unbroken ground plane on the bottom layer. It's broken only in a couple spots, one for the through-holes (which I think should actually be pads) on one of the crystals, and the other is the largish route for VCC to the MCU. Is my ground plane solid enough?

VCC trace close-up

4) Power distribution was a particular problem for me (see my previous question here). In the end I chose to pour a large fill under the MCU, and hook it up to the VCC pin with a large trace. Is this an acceptable strategy for power distribution? If I was working with a 4-layer board, I'd use a whole layer for VCC, but I want to stick with 2-layer for cost reasons.

Overall, how have I done here? Is this likely to boot up, or should I head back to the drawing board?

Best Answer

1) Crystals should not be routed this way. Traces should be shorter and as symmetrical as possible. You should connect capacitors to GND in a single point, so that you are not picking any noise from the ground plate. This is especially important for RTC crystal. With current routing you might get problems with generation start/failure if you are unlucky.

2) Checkout my single-layer board for ARM : http://hackaday.com/2011/08/03/an-arm-dev-board-you-can-make-at-home/ - even this nightmare works (only 1 decoupling cap). Defenitely what you have here will work. You may add some extra caps (like some 25uF electrolytic + 2.2uF ceramic) on the backside of the board, you have plenty of space there, and both VCC & GND together. The only thing I don't like is thin traces to your caps. They should be as wide as possible. In my design, the only capacitor was connected by like 2mm-wide traces.

Also, look at C5: You can move it to the right a little, move via closer to the cap and connect it with short wide track. When you via is under the chip, you cannot have wide tracks. Same for C6 and C7.

Also, if you are going to manufacture this at home,you'll have problems making vias under QFP chips.

3) Ground plate is more than enough. There is no much need to have solid ground plane except a square under chip where all decoupling caps are connected, it won't help with ground noise much. Ground plate is needed for controlled impedance, which is not important in your case. But your GND connection to contacts should be as wide as possible. This is general rule: VCC & GND nets should have wide tracks.

4) Yes, this is perfectly ok for low-speed ARMs.

In my case I even had no back side, and it was still working ;-) The only thing to improve if you are manufacturing on a factory is to have a small VCC square on the bottom layer in the middle of the chip, and connect it to the top using some 4-9 vias instead of 1. For VCC & GND planes you always need to have as low as possible resistances and inductance so that caps can easier filter noise => you need wider and shorter tracks and more parallel vias. But in this specific design it is not a requirement.

So, it will work even now without modifications. After mentioned changes it will be perfect.