The TLC5940 requires a minimum headroom (anode voltage applied to LED) of about 0.7 Volts greater than the LED's Vfwd for driving 60 mA, and 1.2 Volts for 120 mA.
If the headroom is lower than this, the channel is detected as an open LED. Actually, "open" is detected at 0.4 Volts or lower headroom, but that's a minor detail.
In discussions on TI's E2E forum, it has been confirmed from time to time that individual channels (LEDs) can be sourced by differing voltages, as long as the headroom requirement is met.
Another suggested method of reducing the surplus voltage across the TLC5940 driving transistors, is to use an external resistor for each LED, calculated to reduce the maximum current (if the TLC5940 were replaced with a short circuit to ground), to a bit over 10 mA more than the intended LED drive current. That way, the excess voltage is dissipated across each resistor, rather than across the LED driver IC.
First, let's say we work with these two functions:
\$L(n)\$ is the maximum amount of LEDs that can be driven from \$\mathsf{n}\$ pins.
\$p(n)\$ is the minimum amount of pins needed to drive \$\mathsf{n}\$ LEDs.
1:1-method
This one is easy:
$$L(n)=n$$
$$p(n)=n$$
A diode matrix
At first, we need to determine the most efficient diode matrix. For example, you could divide 4 pins into two sets of 2, or one set of 1 and one of 3. Obviously, the amount of LEDs is given by \$\mathsf{length\cdot{}width}\$. We can say \$\mathsf{width=n-length}\$, so the amount of LEDs is: \$\mathsf{length\cdot{}(n-length)=-length^2+n\cdot{}length}\$. Given an \$\mathsf{n}\$, this is a parabola, which has a maximum when \$\mathsf{length=\frac{n}{2}}\$. You can also do this on gut feeling. So, the maximum amount of LEDs is reached when the two sets have an equal amount of pins, or differ only 1, in case of an odd number of pins. We can now say:
$$L(n)=\lfloor{}\frac{n}{2}\rfloor{}\cdot\lceil{}\frac{n}{2}\rceil{}$$
Also, we can now easily understand the function \$\mathsf{p(n)}\$:
$$p(n)=
\begin{cases}
1&\text{ for }n=1\\
\lceil{}\sqrt{n}\rceil&\text{ for }n\gt1
\end{cases}$$
I just included the cases for 1, as this is a special case. Normally, you can just use the second function.
Charlieplexing
In this method, we have two LEDs between every set of two pins. We can calculate the amount of sets of two pins with:
$$(n-1)+(n-2)+\dots+1 = \frac{n\cdot(n-1)}{2}=\frac{n^2-n}{2}$$
Now we can say that:
$$L(n)=2\cdot\frac{n^2-n}{2}=n^2-n$$
We saw that the amount of pairs of pins equals \$\mathsf{n\cdot(n-1)}\$. With some reverse thinking, this leads to:
$$p(n)=
\begin{cases}
1 &\text{ for } n=1\\
2\cdot\lfloor\sqrt{n}\rfloor-1 &\text{ for } n\gt1
\end{cases}$$
I just included the cases for 1, as this is a special case. Normally, you can just use the second function.
Other methods
I'm not aware of any other methods, as of Tuesday march 12, 2013.
Best Answer
The maximum ratings are usually about two things, broadly speaking. One is about local dissipation -- the port pins are often arranged near each other on the die and if you dissipate too much in a small area within the micro, then that area will become a hot spot and there is a limit beyond which you shall not go. Another is about the aluminum interconnects. They design these for a certain current limit. It's likely (though I wouldn't know, specifically, here) that there are some shared current paths for the port and that these also have limits. As I understand it, either of these may have been the actual limiting factor for the absolute maximum specifications you are reading (from which you actually should stay some distance!)
If it is the ability to dissipate power away from the local area, then I would probably assume that you cannot source \$75\:\textrm{mA}\$ and also sink another \$75\:\textrm{mA}\$ on the same port. It would be about dissipation and peak local temperatures, so it would probably mean you can't do both at once. (And you generally shouldn't do it, at all, of course.) If it is about current limits for the shared parts of interconnect, and if the sinking interconnects are in no way shared with the sourcing interconnects, then the answer might be "maybe." But I still wouldn't risk it. And it is almost never about the interconnects, from a few discussions I recall having years ago. It is usually about dissipation. I've only had one case where I actually had to contact the IC designer regarding the worst case design size of their interconnects flowing from one point towards another.
EDIT: I wanted to add a note about one way to examine the absolute maximum specifications to add a little information to how you think about these pin currents.
Each pin has a small impedance to ground, when low, or to the \$V_{CC}\$ rail, when high. The P materials generally have about \$\frac{1}{3}\$rd the mobility of N materials. Mobility directly relates to impedance. So it takes more cross section area to get the same impedance from a PMOS device than an NMOS device, broadly speaking. A manufacturer will sometimes do the extra work (squander more die space) in order to balance both the high-side and the low-side MOSFETs. But usually there is a difference.
It is sometimes instructive for you to actually test this out. The experiment isn't hard to do. Just make the output drive a load resistor (or a pair of them in a Thevenin equivalent) and measure the output voltage. You should be able to work out the current and voltage, knowing your circuit and the voltage measurement, and from this you can work out the driver impedances; both to ground and to \$V_{CC}\$.
My recollection of measuring the impedance of PIC parts was that they present about \$60\:\Omega\$ sinking and about \$100\:\Omega\$ sourcing. (In any case, I don't remember the value being identical.)
Now, let's think about the absolute maximum specs of \$25\:\textrm{mA}\$ per pin and \$75\:\textrm{mA}\$ for a port.
One question arises: What about a device with four ports!! Does that mean I can go drive each port with up to \$75\:\textrm{mA}\$? No. There will also be a device maximum supply current and you should not exceed that, either.
Also, if \$75\:\textrm{mA}\$ for a port, why not \$75\:\textrm{mA}\$ for a pin on the port if the other pins aren't loaded? Well, there may be limits per pin because the metalization to the pin can't handle more and if you drive it with more you will cause the metalization to start migrating over time and that would be a bad thing. Also, all that current in one very tiny place on the die might generate temperatures that are simply too high to be tolerated, continuously. (Implanted ions also can migrate and diffuse outward away from the hot spot, spreading out the designed features and eventually destroying the functionality.) So there are absolute maximums on each pin.
Finally, in the case I mentioned with the impedances I indicated for a PIC I once measured, the heating at \$\frac{75\:\textrm{mA}}{8}=9.4\:\textrm{mA}\$ would then be about \$6−10\:\textrm{mW}\$ per pin (depending on high or low output value), if divided evenly. Say, \$50−80\:\textrm{mW}\$ total for the port. But that becomes almost \$200\:\textrm{mW}\$, if all of it were sourced out of just three pins (staying within the absolute maximums for each pin and for the port.)
I might feel that pushing \$50\:\textrm{mW}\$ for the port would be tolerable (if it bought me something in other trade-offs and didn't risk something important.) But I would definitely not feel comfortable at \$100\:\textrm{mW}\$ per port. And so, broadly speaking, I'd keep the designed pin output currents at around \$6-8\:\textrm{mA}\$ and no more than that. Even though the absolute maximum specifications suggest you can do more.