Electronic – Pipelining and clock frequency issue

fpgaxilinx

  1. Could you please explain me about pipelining in FPGA and how is it done in xilinx system generator design by adding registers and delays in a particular system design?

  2. I have a system design in xilinx system generator. That design meets the timing constrain with 20ns (takes 50MHz clock frequency). However, the FPGA board I use is Virtex 4. It offers 100 MHz (10ns) clock at pin B15. I set 20ns as the FPGA clock period and pin B15 in the System generator token. I was able to generate HDL netlist without any error. However, I wasn't able to get any outputs from the FPGA after I downloaded the bitstream from xilinx ISE. I was wondering it would be the issue with the frequency of the FPGA borad and my design as my design meets only 50MHz NOT 100MHz.

Update with more information

  1. My design:

I was not able to upload the picture. I designed a system to generate UWB signal.

  1. For this design I only managed to reached maximum of 50MHz(20 ns) of clock frequency by adding registers and delay blocks in between the inputs and outputs. I was not able to reduced the time constrain below 20 ns. Because when I tried to reduce it to 10 ns (attempting to reach 100MHz) by increasing the amount of delays I ended up with an error "Resource overmapped", as shown below (Figures are not the same,but similar).

elected Device : 4vfx12ff668-10

Number of Slices: 6690 out of 5472 122% ()
Number of Slice Flip Flops: 20567 out of 10944 188%
Number of 4 input LUTs: 10072 out of 10944 92%
Number used as logic: 9969
Number used as Shift registers: 103
Number of IOs: 7
Number of bonded IOBs: 6 out of 320 1%
IOB Flip Flops: 2
Number of GCLKs: 2 out of 32 6%
Number of DSP48s: 33 out of 32 103% ()

  1. However my Virtex 4 FX12FF668 only offers 100MHz clk at pin B15 (i.e. FPGA clock period (ns) = 10 and Clock pin location = B15 ). I'm clueless for how to change it to 50MHz to suite my design and set it in the sys gen token.

Best Answer

Your design will not function correctly if it runs at 100 MHz but is only spec'd (by the tools) to run at 50 MHz. If it does, then it's a one-off miracle that wouldn't work when you make a change and rerun the tools. Don't do it. Don't even do it if your clock is 100 MHz and the tools tell you the design can run at 99.5 MHz.

To solve your problem you can either write a simple 'divide by power of 2' clock divider to reduce the clock frequency (something like this in Verilog):

reg [n:0] count; 

always @(posedge CLK_100) begin
  count <= count + 1;
end

BUFG bg_0 (.I(count[m]), .O(CLK_DIV));

(where 'm' <= 'n' and 'bufg' is a global clock buffer, and must be used for synchronous designs) or use a Digital Clock Manager (DCM).

Hopefully that solves your pipelining issues as well unless you absolutely have to run the entire design at 100 MHz. Other than pipelining you can consider using FIFOs if you have part of the design running at 50 MHz and the other at 100 MHz, but you'll have to say a bit more about what you're doing to get more meaningful help here.

Related Topic