Electronic – PLL versus putt-putt-skip, putt-putt-wait, fractional-rate division, or other approaches

clockpll

Many applications use PLL's to generate frequencies where long-term frequency accuracy is necessary, but where a certain amount of short-term jitter might be acceptable. I've seen a number of devices with very-low-current low-to-moderate-precision oscillators, and was wondering whether it would be practical for device manufacturers to reduce device current consumption by replacing PLL's with other approaches, such as (note some of the following terms are my own invention, since I don't know of standard names for these techniques):

  1. Putt-putt-wait: If the goal is to have a signal that's N times the input frequency, arrange for the oscillator frequency to be at least N times the input frequency; let the oscillator run for N pulses, stop it until the next input pulse, run for N pulses, stop until next input, etc.
  2. Putt-putt-skip: If the goal is to have a signal that's N times the input frequency, arrange for the oscillator frequency to be at least N times the input frequency; allow N pulses of the oscillator through, then stifle pulses from the oscillator until the next input pulse, then let another N pulses through, etc.
  3. Fractional-rate division: If the goal is to have a signal that's N times the input frequency, arrange for the oscillator frequency to be at least N times the input frequency, and provide hardware to stifle a programmable fraction of the oscillator pulses. Either hardware or software may then adjust what fraction of the oscillator pulses are dropped so as to maintain a consistent phase relationship with the reference wave.
  4. Rate-control dithering: If the goal is to have a signal that's N times the input frequency, allow the oscillator frequency be instantly switchable between a rate that's too fast and one that's too slow, and provide hardware to make a programmable fraction of the cycles be "slow" ones. As above, software or software could adjust this fraction so as to maintain a phase lock if desired.

All of these approaches would have the restriction that the oscillator rate has to be guaranteed to be slow enough not to violate the device's internal cycle timings, but I would expect that in many cases they would make it practical to keep a precise counter/timing reference alive even during sleep mode.

What advantages or disadvantages are there to using approaches like the above in lieu of a PLL? I've never seen the latter two approaches used, but I would think that in many cases they'd provide adequate performance while using a fraction of the power of a PLL (perhaps some "digital PLL"'s use approach #3, but I've never heard of such things operating in sub-mA range)

Best Answer

These methods are used. The TI MSP430, for example, uses something they call a "modulator" which is essentially what you're talking about.

The main advantage is that that they are super simple and they can change their output frequency quickly (without any lock-time or whatever that PLL's require), and without any "glitches".

I'll also mention another method that you didn't mention (directly). It is, essentially, a super simple version of making your approaches 3 and 4. It's called a numerically controlled oscillator. Here's a code snippet in VHDL (but it's generic enough that most should be able to follow):

signal phase :std_logic_vector (n_bits-1 downto 0) := (others=>'0');

process (clk_in)
begin
  if rising_edge(clk_in) then
    phase <= phase + inc;
  end if;
end process;

clk_out <= phase(phase'high);

Basically, we have an n_bit long accumulator (a.k.a. counter). On each clock, we add 'inc' to the accumulator. The most-significant-bit of the accumulator is output as the new clock signal. The output frequency is calculated like this:

Fout = Fclk_in * inc/(2^n_bits)

Where Fclk_in is the input clock frequency, inc is the value added to the accumulator, etc. Fout can be anything less than Fclk/2. For more accuracy, or a lower output frequency, you need more n_bits.

The output of this logic is essentially a jittery clock, where the jitter is about 1 clk_in period. The frequency and duty cycle will be dead-on (given n_bits and the clk_in period).

I have frequently used this logic to generate baud rates and other slow but accurate clocks. Since I work with FPGA's and not too many ASIC's I normally keep the logic synchronous with respect to clk_in and output a clock enable signal or something-- but the same concepts apply.

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