Electronic – PMOS Gate Driver using BJT


I'm (again) looking at high-side load-switching. The load shall be switched on with a controlled rise-time (=limited inrush current) and be switched-off quickly when a controller (not shown) detects an error condition.

My problem with the typical slew-rate control circuit is the dependence of output-slew rate to supply voltage level. Also turn-off is slow since the gate is pulled up only by R2.


simulate this circuit – Schematic created using CircuitLab

What I came up with in response is the following schematic:


simulate this circuit

Q2 is there for fast turn-off. Addition of Q3 seems to solve the problem of supply dependent rise-rate – at least in LTSpice. However, frankly don't know why.

Apparently I'm using Q3 not as a switch, but in it's linear region to "regulate" the current through R2, but the component values are made up by trial and error and I would like understand the matter. Could someone also comment on temperature influence?

Best Answer

Q3 is operating in one of two distinct modes, depending on whether its collector is higher than or lower than the voltage on the EN signal.

When the collector voltage is higher (right after turn-on), it functions as a constant-current sink, with the current determined by the emitter voltage (which is one diode drop below the base voltage) across R2.

However, when the collector voltage drops too low to sustain this voltage across R2, then the base and emitter voltages also drop and Q3 just functions as a saturated switch.