Electronic – Prevent ISE from bitswapping the configuration file

Quick answer: No such list exists, anywhere.

Long answer: I could tell you, but then I'd be wrong. I've been using Xilinx tools for the past 15+ years and every time they come out with a new version (or even a new service pack) things change. Sometimes even just changing various XST/MAP/PAR options will cause new files to be generated. So even if I did give you a list it would likely be out of date or just wrong.

I've created my own makefiles for building my FPGA's (I'm not using ISE's GUI environment), and it's fairly well documented what the input files to the various tools are (XST, MAP, etc). Everything else is not required and thus doesn't need to be checked into the source control system. My makefiles have a "make clean" option that removes all of the extra files. So when Xilinx releases a new version I simply recompile and the "make clean". Any file that remains (and isn't obviously something I need) is considered to be junk, and I add those files to the "make clean" list of things to delete.

You want them to output low, so go ahead and make them outputs in your VHDL. Then they won't get optimized out.

A single net called "RESERVED(xx downto 0)" would do it. Tie it low in your VHDL, and constrain it to the unused pins just as you would any other signal.

This is the most portable way, really.