Electronic – Problem in synthesizing

vhdl

I'm trying implement structural implementation of ring counter.
I get this error:

ERROR:Xst:528 – Multi-source in Unit <ringcounter> on signal <count<3>>; this signal is connected to multiple drivers.

I could simulate it successfully.This module is a part of the project I'm implementing!..

Here is my VHDL code:

entity DFF is
    Port (
      reset : in STD_LOGIC;
      clk : in  STD_LOGIC;
      D : in  STD_LOGIC;
      Q : out  STD_LOGIC);
end DFF;

architecture Behavioral of DFF is
begin

    process(clk,reset)
    begin
        if reset = '1' then
            Q <= '0';    -- clear register
        elsif (clk'event and clk = '1') then
            Q<=D; --positive edge of clock is used
        end if;
    end process;

end Behavioral;

--Code for ring counter

entity ringcounter is
  Port ( reset : in STD_LOGIC;
         clk : in  STD_LOGIC;
         count : out  STD_LOGIC_VECTOR (3 downto 0));
end ringcounter;

architecture Behavioral of ringcounter is

    signal q0,q1,q2,q3 : STD_LOGIC : = '0'; ---initialising the signals

    --signal temp :STD_LOGIC :       = '1'; --not using it as of now.

    component DFF is
        Port ( reset : in STD_LOGIC;
              clk : in  STD_LOGIC;
               D : in  STD_LOGIC;
               Q : out  STD_LOGIC);
    end component;

begin

    q3<= '1';

    DFF1: DFF port map(reset,clk,q3,q0);

    DFF2: DFF port map(reset,clk,q0,q1);

    DFF3: DFF port map(reset,clk,q1,q2);

    DFF4: DFF port map(reset,clk,q2,q3);

    count <= q3&q2&q1&q0;

end Behavioral;

Whats going wrong?

edit

I did the changes as suggested but while simulating, the output are not getting updated for ring counter output even though I specify clock! The output is still undefined!

below is the modified code

entity DFF is
    Port ( reset : in STD_LOGIC;
           clk : in  STD_LOGIC;
           D : in  STD_LOGIC;
           Q : out  STD_LOGIC);
end DFF;

architecture Behavioral of DFF is
begin

    process(clk,reset)
    begin
        if reset='1' then
            Q <= '0';    -- clear register
        elsif (clk'event and clk='1') then
            Q<=D; --positive edge of clock is used
        end if;
    end process;

end Behavioral;


------------CODE OF RING COUNTER-----------------------

entity ringcounter is
    Port ( reset : in STD_LOGIC;
           clk : in  STD_LOGIC;
           count : out  STD_LOGIC_VECTOR (3 downto 0));
end ringcounter;

architecture Behavioral of ringcounter is

    signal q0,q1,q2 : STD_LOGIC := '0'; ---initialising the signals

    signal q3 :STD_LOGIC := '1';

    component DFF is
        Port ( reset : in STD_LOGIC;
               clk : in  STD_LOGIC;
               D : in  STD_LOGIC;
               Q : out  STD_LOGIC);
    end component;

begin

    DFF1: DFF port map(reset,clk,q3,q0);

    DFF2: DFF port map(reset,clk,q0,q1);

    DFF3: DFF port map(reset,clk,q1,q2);

    DFF4: DFF port map(reset,clk,q2,q3);

    count <= q3&q2&q1&q0;

end Behavioral;

yes I did specify reset. That time it'll only set the value to zero and no transition happens which is very obviously seen as I tried inserting a flip flop with preset input which will pump a 1 value to the flipflops ring!..I'm just simulating it. How do I make the value to shift after reset/preset?Am I missing some procedure?…

SO the problem now is
How do I initialize all the flipflops and start shifting after, in sequence using the simulator??…

I have tried using behavior model not using DFF.
Below is the codefor the same.

entity ringCounter_BehaviorModel is

Port ( CLK : in  STD_LOGIC;

       CLR : in  STD_LOGIC;

       Q : inout  STD_LOGIC_VECTOR (3 downto 0);

       NQ : inout  STD_LOGIC_VECTOR (3 downto 0));

end ringCounter_BehaviorModel;

architecture Behavioral of ringCounter_BehaviorModel is

begin

process(CLK, CLR)

begin
if (CLR ='0') then

          Q<= "1000";                   

      elsif (CLR ='1') then

if CLK'event and CLK='1' then

        Q(0) <= Q(3);

        for i in 0 to 2 loop

        Q(i+1) <= Q(i);

        end loop;

    end if;

end if;

end process;

end Behavioral;

My question is when I simulate it I force the value of clr to 0 in order to initialise the counter to 1000 and I give clock signal to the clock input.
After I click on run I could see the values of Q as 1000 but the values remains same even when I observe the clock pulse varying between 0 and 1.

when I rerun all the values are lost and I have to force the values all over again..

In the case of clr = '1' initialization doesn't happen and no hope of shifting the desired values.
Am I missing somepoint in procedure or should I modify the code or will the observation made is just fine in case of simuation?

So the summary of problem remains still same and is just that to initialise the ring counter and start rotating around the system.

Best Answer

Inside ringcounter, q3 is being assigned by both the concurrent assignment q3<='1' and DFF4. You can't have both at the same time.