Basically, I have a question regarding the timing of the 74HC574 octal latch. According to the timing diagram, the data pins must be set for so many nanoseconds before the latch pin (rising edge triggered) is pulsed or else the data may not be retained as it should be.
Because the Z80 cannot change the states of its data pins (in which case I could set the data pins with one command, then pulse the latch pin afterwards) this leads me to believe I will have to purchase a parallel IO chip for the Z80 (which I don't want to have to do as that is yet another chip I'll have to add to the motherboard, making it even larger and/or more crammed for space).
BUT, I'm wondering if the I/O address decoding logic will create enough of a delay, as AND gate ICs will create a very small delay (in the nanosecond range as well). The data bus will be directly connected to the 74HC574 and therefore will change the data pins instantly, but the signal which will pulse the data latch pin will have to go through a few AND gates of glue logic which might create enough of a delay that the data pins will be set long enough before the latch pin is pulsed.
I apologize for not being specific in the title, although if you read this you probably agree that my specific question takes a paragraph to explain.