Electronic – Random Access Memory Modelling in Verilog

ramverilog

Is there a better/alternative way of modelling RAM Memory in Verilog other than declaring it as an array of registers? Most of the sources I referred to have memories coded in the following manner.

output reg [WIDTH-1:0] word_out; 
input [WIDTH-1:0] word_in, cpu_addr;
input reset, we, clk;
reg [WIDTH-1:0] chip [0:DEPTH-1];

always @ (posedge clk)
begin
  if (!reset)
    begin
      if (we)
        begin
          chip[word_addr] <= word_in;
          word_out <= word_in;
        end

      else
        word_out <= chip[word_addr];
      end
    end

Is there an alternative to this, probably using flipflops or something?

Best Answer

I believe you are aware that there are different types of modelling systems in HDLs:
1) Behavioral modelling - describing the behaviour of the system like a computer program
2) Structural modelling - interconnecting primitive and complex components by signals
3) Mixed - combining (1) and (2)

If you are more into behavioral - use the array representation. It is a best abstraction for "program-like" paradigm.
If you like more interconnecting existing components - you can model yourself, download or use a RAM from some standard library, that will be represented as a component with inputs and outputs for you.

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Electronic – how many bits a random-access memory’s cell contains

There is almost no chance that your memory is bit-addressed. The most likely situation is that your addresses are byte-addresses. And when you get the value of a 32-bit variable, the question is whether that address points at the Most Significant Byte or the Least Significant Byte of that 4-byte value - which is architecture dependent (e.g. x86 is little-endian, while MIPS is big-endian).

To give you an example in C, assuming your variable var has the value 0xDEADBEEF it might be stored in memory in one of two ways:

Big-Endian (because the address 0x125 points to the MSB)

-------------+--------+--------+--------+--------+
base address |              offset               | 
-------------+--------+--------+--------+--------+
             |    0   |    1   |    2   |    3   | 
-------------+--------+--------+--------+--------+
    0x125    |  0xDE  |  0xAD  |  0xBE  |  0xEF  |
-------------+--------+--------+--------+--------+

or Little-Endian (because the address 0x125 points to the LSB)

-------------+--------+--------+--------+--------+
base address |              offset               | 
-------------+--------+--------+--------+--------+
             |    0   |    1   |    2   |    3   | 
-------------+--------+--------+--------+--------+
    0x125    |  0xEF  |  0xBE  |  0xAD  |  0xDE  |
-------------+--------+--------+--------+--------+

As the granularity of access to the memory at the instruction set level is likely no smaller than a byte, if you want to modify individual bits, you need to read from the memory at its minimum granularity (likely a byte), modify its contents with bit-manipulation operations (|, &, ~, etc.), and write back the memory.

Electronic – Verilog asynchronous reads of regs – and design question

Your code simulates two multiplexers. These are actually asynchronous components. The fact that Verilog requires data1_temp and data2_temp to be declared as reg's is a quirk of Verilog syntax and your choice of coding style, and doesn't mean these signals would be the outputs of storage elements in a physical implementation.

If you want to capture these values in actual registers, you need to add those explicitly:

reg [7:0] data1, data2;
always @(posedge someclock) begin
    data1 <= data1_tmp;
    data2 <= data2_tmp;
end

But I would like to know what this mini register file would be made of in hardware. Particularly, the 4x8 bit array consisting of k0,k1,k2,k3.

You haven't shown how these variables are assigned, so it's not possible to say how they are implemented. As your code showed, just declaring them as reg doesn't guarantee they are implemented with actual storage elements. If you assign them inside a block that begins always @(posedge clk) then very likely they are flip-flops, but there are ways you could code them that would make them synthesize differently.

I thought when it came to registers and arrays like this, you need a clock to read out data, like RAM?

You need a clock to update a (physical) register. You can read it out at any time. For example:

wire [8:0] sum;
assign sum = k0 + k1;

is perfectly valid code. sum will change whenever any of its inputs changes. If k0 and k1 are the outputs of flip-flops, their values will only change when there is a clock edge.

For another example, you could equally well describe your multiplexers with code like this:

reg [7:0] k0, k1, k2, k3;
wire [7:0] data1_tmp;
reg [1:0] reg1;
// k<n> and reg1 are assigned elsewhere.
assign data1_tmp = (reg1 == 0) ? k0 :
                   (reg1 == 1) ? k1 :
                   (reg1 == 2) ? k2 : k3;

how do I read from this tag_array and do the comparison all within the same clock cycle?

Let me repeat a key point for emphasis: You need to use a clock to assign a new value to a register (an actual hardware register or group of flip-flops). It's output is available at any time.

RAMs are different and how you access the contents of a RAM will depend on details of the type of RAM you use.

I got confused because frankly I don't know enough about memory hardware and how that's possible.

Another key strategy: When you are learning digital logic, I recommend you learn about the physical hardware first, and then work out or study how to simulate it in HDL second. So first, learn what a physical flip-flop is, then learn the standard Verilog methods of describing a flip-flop. Especially if you are trying to write HDL for synthesis, trying to write good code before you learn the capabilities of the underlying hardware will lead you down a lot of dead-end paths.

Best Answer

Related Solutions

Electronic – how many bits a random-access memory’s cell contains

Electronic – Verilog asynchronous reads of regs – and design question

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