I designed a Arduino shield compatible board around the NXP LPC4337JBD144. so far I have been unable to get the first revision to program.
In the first design the JTAG header was not setup correctly, there were no bypass capacitors, the USB did not have all the pullups/pulldowns it needed, the DBGEN and TRST pins were not broken out to jumpers, and the Ethernet section did not follow spec as strict as it should have. I have able to add all the pullups to the JTAG and pull the DBGEN high and the TRST low by modifying the PCB with external jumper wires and resisters. I am still unable to program it with my JTAG.
I should note that the rev one PCB is only populated with what is necessary to get the chip programming and running, no additional hardware passive or active. I have tested that I am getting the correct signals from the JTAG and they are going to the right pins. I checked the crystal as well but I don't get a signal because the crystal will no initialize until the chip is programmed because the first thing that runs in a system configuration routine that sets up all PLLs and external oscillator settings. Everything on the first revision PCB has been check thoroughly with an oscilloscope, JTAG signals, crystals, and power section.
That being said I have been battling with this first revision for several weeks, I have tried everthing that NXP support has recommended, I have reviewed the schematics for several evaluation boards from NXP, Keil, and Hitex modifying my PCB along the way to bring it up to the ARM standard spec to no avail.
At this point I am convinced that the design is flawed in too many ways putting it way out of the standard specifications for an ARM Cortex M4 that it cannot be fixed with external modification to the PCB and that second revision of the design needs to be tested. This is a very time sensitive design, I was hoping to at least get the first one working then have the second revision be a fine tuning process. That being said I need to get a new design out to the fab house to keep my professors happy. I'm looking for constructive feedback on my new design, I have spent about two weeks looking through this design on my own and with the help of others in attempts to find anything that could be a serious potential problem down the road. I have been double checking the reference schematics and datasheet and I personally haven't detected any problems so far (most of my previous design work has been with AVRs).
EDIT:
My board is 4 layers, the two outer layers are for signals and the two inner layers are a ground plane and a power plane. Right now I have the negative space on the two outersignals filled in with a ground fill polygon, could that cause some problems with the board such as ground loops?
Below I have attached the smart PDF for my Altium Project it includes the schematic and PCB design. https://www.dropbox.com/s/qb9ptr67v6msmh0/Abstract%20Hardware%20Device.pdf
Altium PCBdoc: https://www.dropbox.com/s/s7s0aw3yuh4va3g/Abstract%20Hardware%20Device%20PCB.PcbDoc
EDIT2:
share link updated to Dropbox one.
Altium PCBdoc shared.
Best Answer
When I review schematics/PCB during my day job, for a design like this, I would spend about 8 to 16 hours going over it. Clearly I cannot do that here. Further, I cannot give you a lesson in EE for each thing that is wrong in the design. And to make things worse, EE.SE is not really suited for a back-and-forth dialog that is normally required for a review like this. So here's what we'll do. I'll do a quick review of the design and put the issues that I spot in this answer. You read that, do some studying on your own, and if you still don't understand then you need to post a new question (not a comment on this answer). Here goes:
You need some EMI filtering on the +3.3v to the center tap of the Ethernet transformers. Some sort of ferrite bead + cap(s).
You need ESD protection diodes on the Ethernet signals to U4.
10 pF decoupling cap on X2 is astonishingly small. Use 0.1 uF.
Ethernet termination resistors, R42-45, must be at least 0805's to handle the wattage required. I can't tell what size you are using.
Something doesn't look right with the Ethernet TX CLK signal. I don't think you should have it connected to three chips (Oscillator, Phy, and MAC). Double check that in the Phy/Mac reference designs.
Put a 0.1 uF cap on the "input" side of your ferrite beads.
The note "crystal oscillator needs to be 12 mm away from the phy" is a HUGE red flag to me. It makes me think that something is not right, but I don't know what. If this were a normal design review I would grill you over this.
You should filter or buffer reset signals that go over connectors (like SHIELD_RESET). This is a huge way for an ESD event, even 6+ feet away, to cause the PCB to reset.
You should have a 0.1 uF decoupling cap(s) at every connector to reduce the AC signal return path for signals on the connector.
It doesn't look like you have enough input caps on the DC power input. I could be wrong, however, since I can't read your schematics that well (stupid web-app).
You might need more caps on the output of your voltage regulators. I didn't check, however, because I don't have time to read the datasheets.
It is hard to really judge the PCB layout without looking at the design in the CAD software (Altium). But I see enough issues that the whole design needs to be scrutinized before being send out.
Vias need to be spread apart so they don't cause slots in the power/gnd planes.
Additional gnd planes on the top and bottom layers is not adding much to the design. It is worth it to just remove those.
Do you have proper signal termination on the MII signals between the MAC and Phy?
Have you verified that the PCB layer stackup is correct for the trace impedance you want and the signal termination that you have>
You have signals crossing voids in adjacent power/gnd planes. This is a HUGE no-no.
Your signal GND plane and your chassis-gnd planes overlap. Never, ever do this. (Disclaimer: I could be looking at the plots wrong.)
So there you go. Good luck!