clock-speedenergyfrequencyi2cpower-consumption
Referring to just what the I2C lines draw, am I wrong thinking that the higher the clock frequency the shorter the time there will be (the same amount of) current flowing through the pullups and thus lower power consumed?
side qeustion
I don't think I am going to reach 100 kHz, that's way over the limit of my hardware. I am alternating between about 32 and 4 kHz. Will the same resistor value (3.3k @ 3V) be good for both?
If you are going to run an I2C bus with mixed speeds, and you have devices on the bus that can only work at 400 KHz and below, then they must be disabled somehow (e.g. powering them down, so their I2C bus leads will be tristated) when running the bus at the 1 MHz speed, since they will not be able to parse the high-speed addresses and may respond incorrectly.
I can think of three possible mechanisms that may result in the system starting to work if you touch the SCL line with an oscilloscope probe. All three indicate a fault in the unit.
First, it may be a mechanical issue such as a bad solder. When you poke it with the probe, it may repair the connection and signal starts to flow.
Second, it may be a noise issue; crosstalk, coupled noise from any source, and the application of the probe's capacitance dampens that noise. But that would mean that your I2C bus's pull-up resistors are far too small. They should be something like a few kilo-ohms.
Third, your SCL and SDA signals might be switching at the same time, which is a no-no in I2C bus. You shouldn't change both signal states in the same operation; there should be a time delay between any edge in SDA signal to any edge in SCL signal. If the both switch at the same time, the application of the probe capacitance to SCL may delay the SCL edge enough that the I2C device's input data stabilizes before it sees the edge in the clock signal. And this failure mechanism would indicate an error in your microcontroller code.
Edit: For a reference, here is a picture of a proper i2c waveform from the datasheet of the microcontroller which the asker is using.
Image source: LPC1769 datasheet page 59
Best Answer
Higher clock frequency usually require lower pull-up value, thus increasing the current.
Increasing the clock frequency from 100kHz to 400kHz usually requires the pull-up to be reduced with a factor of 4-5.
Since the power is inverse proportional to the resistance the power consumed will be almost the same.