Electronic – Relationship between reset pins and SWD functions (ARM Cortex M0)


On many microcontrollers or other devices without JTAG/SWD functionality, there is a reset pin which when low unconditionally and asynchronously forces everything into a known state. On devices with JTAG or SWD functionality, however, things seem to be more complicated since it's possible to perform some JTAG/SWD functions while the reset pin is asserted.

I have some Freescale KL15Z-based boards which include the SWD pins on a connector with the reset line and some other diagnostic I/O pins. Occasionally when connecting or disconnecting a cable, the parts seem to get into a weird state such that even reset won't kick them out. I'm wondering if some stray pulses on the SWD pins might be putting the device into an "ignore the reset pin" state. I have found that when using the debugger, I seem to have frequent difficulties getting the devices to reset reliably; I don't know if the issues may be related.

What is the relationship between the reset pin and the SWD functionality? Conceptually it would seem most helpful to have a design where any falling edge on reset would be guaranteed to actually reset everything, and SWD communications which were supposed to happen before user code startup could be performed with reset held low, but I don't think that's how the Freescale KL15Z chips actually work. What's the best way to solve such reset-related problems with the Freescale or similar parts?

Best Answer

Reset pin is often not needed, because controller is possible to reset using debug registers.

Only one case when is necessary is connection under reset, this mean that if SWD signals are shared with other functionality on board (forexample SWDIO or SWDCLK is set as output), then only way to access MCU is to put MCU in to reset (at this moment are some debugging registers accessible over SWD) and set HALT/STOP program flag with debug registers over SWD, then leave reset pin and at this moment it is possible to flash MCU.