Electronic – RF 50 ohm dumthe load PCB design

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I am a rookie on both RF and PCB design and I am currently trying to do a 50 ohm 11 watt dummy load project for 100MHz-1GHz.

My calculations are done for the load but I have some questions about designing the PCB.

My new design is as below:

enter image description here

My instructor keeps saying that :

''There is a problem with lining up resistors on a row, because you will see a high impedance with reflections on first resistor, then traveling to the next, and the next … Try designing so that the signal reaches all resistors at the same time. This is difficult with so many resistors. If the attenuator is then directly connected to the same point your series resistor can be of high impedance without affecting signal, because of the short length.''

I don't know how to do this and out of ideas, I tried to do it as a circle around the connector but still not accepted.

Attenuators written as AT1,AT2,AT3. The other resistors are for the load.

Project Specification:

  • The power I am trying to terminate is 5-10 watts.
  • SMD resistors are 560Nohms 1 watt resistors and the signal strength should not exceed -10dBm that is why I am using an 50dB attenuator, to achieve the desired signal strength.

PCB design Specification:

  • Trace Width = 0.5mm
  • Dielectric Thickness = 0.3mm
  • Trace Thickness = 0.036mm
  • Substrate Dielectric (Ɛr) = 4.6
  • Total board thickness = 0.39mm
  • Size of the resistors (x,y) = (6.4,3.2)mm
  • Dimensions of the board are (x,y) = (7.5,10)cm

EDIT

So I decided to do it as a star or circle shaped design to make the lines equal to each other. Here is what it looks like:

enter image description here
Schematic of The Dummy Load and Attenuators

I just draw this schematic to show how my circuit looks like there might be errors.

Best Answer

The biggest problem you have is the parallel connection of all those 560 Ω resistors. You obviously need to space them apart so that they can all dissipate their heat. However to parallel them at RF, you need 560 Ω transmission lines, and you can't get impedance that high on microstrip, especially the very thin dielectric you've chosen. The eleven lines in parallel will cause a very large shunt capacitive defect, giving you an increasingly degraded return loss as the frequency rises.

This is how I'd approach the circuit

schematic

simulate this circuit – Schematic created using CircuitLab

Resistors are chosen from the E24 series, nearest to the value that would actually give 50 Ω match and equal power dissipation. As a result of that approximation, the final DC resistance comes out to about 49 Ω. Each horizontal line is a length of transmission line, with the approximate impedance (rounded to integer) above it. You'll note they are all 'reasonable' values, in the ballpark of 50 Ω, so straightforward to fabricate on the board. As transmission lines, they can be any length, allowing you to space the resistors at will around the board.

There are some practical details that will affect the high frequency match. High value resistors tend to be a bit capacitive, low value resistors a bit inductive, so this layout would only be a first cut, and measurement, or detailed modelling with data for those specific devices, would be needed to tweak up the match. There is plenty of scope to change the impedance of the series lines slightly to compensate for the parasitics of the components.

Note that the signal decreases along the chain, so R11 provides the ideal place to feed the final instrumentation attenuator, with a slight modification of value as required.