I'm late to the game, but I'll give it a shot:
1- It appears that for a lot of manufacturing houses, 105 microns is as high as its gets. Is that correct or are higher thickness possible?
Some fab shops can plate up internal layers. The tradeoff is usually larger tolerance in the overall thickness of the board, e.g. 20% instead of 10%, higher cost, and later ship dates.
2- Can the copper in the inner layers be as thick as the copper at the top and bottom of the board?
Yes, though inner layers do not dissipate heat as well as outer layers, and if you're using impedance control, they are more likely to be striplines than microstrips (i.e. using two reference planes instead of one). Striplines are harder to get a target impedance; microstrips on the outer layers can just be plated up until impedance is close enough, but you can't do that with internal layers after the layers are laminated together.
3- If I'm pushing current through several board layers, is it necessary or preferred (or even possible?) to distribute the current as equally as possible throughout the layers?
Yes, it is preferred, but it is also difficult. Usually this is only done with the ground planes, by way of stitching vias and mandating that holes and vias connect to all planes of the same net.
4- About the IPC rules regarding trace widths: Do they hold up in real life? For 30 Amps and a 10 degrees temperature rise, if I'm reading the graphs correctly, I need about 11mms of trace width on the top or bottom layer.
The new IPC standard on current capacity (IPC-2152) holds up well in real life. However, never forget that the standard does not account for nearby traces also generating comparable amounts of heat. Finally, be sure to check voltage drops on your traces as well to make sure they are acceptable.
Also, the standard does not account for increased resistance due to skin effect for high-frequency (e.g. switching power loop) circuits. Skin depth for 1 MHz is about the thickness of 2 oz. (70 µm) copper. 10 MHz is less than 1/2 oz. copper. Both sides of the copper are only used if return currents are flowing in parallel layers on both sides of the layer in question, which is usually not the case. In other words, current prefers the side facing the path of the corresponding return current (usually a ground plane).
5- When connecting multiple layers of high current traces, what's the better practice: Placing an array or grid of vias close to the current source, or placing the vias throughout the high current trace?
It's best (and usually easier from a practical point of view) to spread the stitching vias out. Also, there is an important thing to keep in mind: mutual inductance. If you place vias that carry current flowing in the same direction too close to each other, there will be mutual inductance between them, increasing the total inductance of the vias (possibly making a 4x4 grid of vias look like a 2x2 or 1x2 at decoupling capacitor frequencies). The rule of thumb is to keep these vias at least one board thickness from each other (easier) or at least twice the distance between the planes the vias are connecting (more math).
Finally, it is still wise to keep the board's layer stackup symmetric to prevent board warpage. Some fab shops may be willing to go to the extra effort to fight the warpage from an asymmetric stackup, usually by increasing lead times and cost since they have to take a couple tries at it to get it right for your stackup.
A guard ring is traditionally used to protect high impedance nodes in a circuit from surface leakage currents. The guard ring is a ring of copper driven by a low-impedance source to the same voltage as the high impedance node. This would typically be the input pin of an op-amp.
Here's an example of a classic guard ring layout for a metal can op-amp from National Semi's AN-241:
And here's an example of how it would be connected, from Analog's Analog Dialogue magazine:
The key feature is that the guard ring is connected to a node that will be driven to the same voltage as the high impedance node being protected, but with a much lower source impedance.
Note that not all vendor websites are created equal. Microchip's AN1258 recommends using the high-impedance net to create a guard ring around the low impedance nets --- don't do this.
Now to your specific case. While the undriven side of your capacitor is not strictly a low-impedance node, since the ammeter itself should provide a fairly low impedance path to ground when you're measuring, it's still going to cause measurement errors if any current should try to reach ground through that node instead of by another path. It wouldn't hurt to add a ring around the node like this:
Unlike in another answer, I wouldn't include the driven side of the capacitor within the ring, since that's a low impedance node, being driven to a fairly high voltage. However, you've indicated the net in question isn't even physically located on the PCB, so this advice is largely moot. Being as the high impedance net is basically floating in air, it should be well-protected from leakages in any case.
I believe the first image you posted is meant to accommodate a machined EMI shield that is screwed down. You can see that it would provide EMI shielding as well as isolating the circuits from each other. The metal is plated so it makes contact with the shield (maybe just ENIG).
The second one you posted is for a cheaper TI part. It looks like this design could accommodate a soldered down sheet metal shield for EMI. These are much cheaper and if this small can be placed during automated assembly.
It's easier to take off the more expensive screwdown shield, but you can get some sheet metal ones with pull off tops. They also make board clips now that you can put on your board and snap the shield into.