Electronic – RMII MAC side routing and signal integrity

I think you're on the right path, a couple of notes,

1) With a signal trace between two planes, the return current will split between the two planes, even if one of the planes is split. The return current cannot "see the future" and decide ahead of time which plane to return on. It will return above and below the trace until it sees the split at which point is says "oh crap!" and pays you back by possibly causing you to fail FCC testing. So you want to avoid running traces over plane splits even if another adjacent plane is not split. You can deal with splits with capacitors and such but this type of solution is less than ideal. I'd focus on always avoiding running a trace over a plane split on an adjacent plane.

2) Wide return paths on DC signals don't really matter.

3) You asked about two signal layers sharing the same plane. Usually, this is not a big deal if done properly. What many people do is use one of the layers as a "horizontal" signal layer and the other as a "vertical" signal layer so the return currents are orthogonal to each other. It is very common to route two signal layers for each plane, and use this horizontal/vertical technique. The most important thing to remember is to not change reference planes. Your setup could be a little tricky because going from the bottom layer to the 4th layer adds another return plane. More typical 6 layer boards are

1)ASignalHor 2)GND 3)ASignalVer 4)BSignalHor 5)POWER 6)BSignalVer

If you need smaller additional planes, like under the micro, these would usually be placed as an island on one of the signal layers. If you need to use more power planes, you might want to think about going to 10+ layers.

4) Plane spacing is important, and can have huge impact on performance, so you should specify this to the board house. If you take the example 6 layer stackup I mentioned above, spacing of .005 .005 .040 .005 .005 (instead of standard stackup with equal distance between layers) can make an order of magnitude improvement. It keeps the signal layers close to their reference plane (smaller loops).

1) Three layer boards are incredibly uncommon and difficult to manufacture, and will cost you a lot more. Make a four-layer board instead. That being said, asymmetrical ground plane distances is not a problem, but will affect impedance. Use the Saturn PCB Toolkit to get your required trace widths and dielectric thicknesses. That tool has an asymmetric edge coupled microstrip impedance calculator built in.

2) The exact distance between the two conductors in a pair isn't as critical as you might think, provided they are well away from other conductors and polygons that are not part of the differential pair. Design to make sure the tracks are as close together as possible and meet impedance requirements.

3) Trace lengths between separate LVDS pairs are most important when your receivers are very time-dependent (i.e. you need to make sure all of your data reaches the receiver before the clock triggers. Otherwise you could lose data). Actual length requirements depend greatly on the transmitters and receivers you're using, as well as the frequency of the transmitted signals. When it comes to the conductors within a single pair it becomes much more critical. How critical depends, once again, on the frequency of the transmitted signals and how good your receivers are at detecting transitions.

4) Without providing us with your design it is impossible for us to critique it.

5) Right The First Time by Lee Ritchey is one of the best books I have ever found for designing for high-speed signals. It has a LOT of in-depth descriptions, explanations, tips, tricks, etc that are immensely useful. I cannot recommend this book enough.

While I have done some high-speed design I am by no means an expert, so I am open to corrections and additions to this post.

Marcus is right, though, each one of these questions could be given its own post and you'll get more in-depth answers that way.