Electronic – Running VHDL process off an input clock higher than the FPGA clock

clockfpga

I have the following dev FPGA board:

Altera Cyclone II EP2C5T144 FPGA Dev Board

This FPGA has a 50mhz clock. However I want to interface with an external FTDI device that runs at 60mhz. I am driving my VHDL process off the 60mhz clock as an input.

My question is can this safely work? I'm thinking its not safe because the FPGA flip flops are running at 50mhz but its being "forced" to run at 60mhz since the process is driven off this input clock pin?

Should I be removing the FPGA oscillator and connecting it to the existing FTDI oscillator? I'm still very new to this so sorry if this is really silly question :).

Best Answer

Most FPGAs have multiple clock capable pins, and you decide which one drives which registers (usually with some constraints, see your parts reference manual).

Just because you have a clock hooked to one of the clock capable pins does not mean you have to use it....

I would hook your 60MHz to a clock capable IO pin and then run all your logic off that clock and just ignore the 50Mhz one. Note that typically NOT all IO pins are clock capable but there are usually a few per IO bank that are (In various ways, again see the device manual), fpga clocking is usually slightly separate routing wise from the logic itself.

The reason to ignore the 50Mhz one is that due to something called metastability running signals between logic working at different clock frequencies is something of an advanced subject, not usually hard, just not something you need to be dealing with if clocking is still a mystery.

60MHz is basically DC in FPGA clock terms, but you do still need to define your clocks and constrain timing for the new rate. Unless you have a STUPID amount of combinatorial stuff between the registers, 60MHz is unlikely to cause you serious problems closing timing.

Related Solutions

Electronic – Can an FPGA design be mostly (or completely) asynchronous

A short answer would be: yes; a longer answer would be: it is not worth your time.

An FPGA itself can run a completely asynchronous design no problem. The result you get is the problem since timing through any FPGA is not very predictable. The bigger problem is the fact that your timing and resultant design will almost definitely vary between different place and route sessions. You can put in constraints on individual asynchronous paths making sure that they do not take too long, but I'm not quite sure that you can specify a minimum delay.

In the end it means that your design will be unpredictable and potentially completely variable with even a slight design change. You'd have to look through the entire timing report every time you change anything at all just to make sure that it would still work. On the other hand, if the design is synchronous, you just look for a pass or fail at the end of place and route (assuming your constraints are setup properly, which doesn't take long at all).

In practice people aim for completely synchronous designs but if you need to simply buffer or invert a signal, you don't need to go through a flip flop as long as you constrain it properly.

Hope this clears it up a bit.

Electronic – Pipelining and clock frequency issue

Your design will not function correctly if it runs at 100 MHz but is only spec'd (by the tools) to run at 50 MHz. If it does, then it's a one-off miracle that wouldn't work when you make a change and rerun the tools. Don't do it. Don't even do it if your clock is 100 MHz and the tools tell you the design can run at 99.5 MHz.

To solve your problem you can either write a simple 'divide by power of 2' clock divider to reduce the clock frequency (something like this in Verilog):

reg [n:0] count; 

always @(posedge CLK_100) begin
  count <= count + 1;
end

BUFG bg_0 (.I(count[m]), .O(CLK_DIV));

(where 'm' <= 'n' and 'bufg' is a global clock buffer, and must be used for synchronous designs) or use a Digital Clock Manager (DCM).

Hopefully that solves your pipelining issues as well unless you absolutely have to run the entire design at 100 MHz. Other than pipelining you can consider using FIFOs if you have part of the design running at 50 MHz and the other at 100 MHz, but you'll have to say a bit more about what you're doing to get more meaningful help here.

Best Answer

Related Solutions

Electronic – Can an FPGA design be mostly (or completely) asynchronous

Electronic – Pipelining and clock frequency issue

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