Electronic – Sample and hold: fast switching

The op-amp circuit following the sample and hold is intended to have a gain of two and I think this over complicates things with the mid-rail generator formed by R1 and R2. Try this for size: -

• Get rid of R1, R2 and R4 - just remove them and don't connect anything in their place.
• Get rid of D1 and short it out - it's just adding an error that is not needed.

Now, if you have 3V on the input and you sample it, 3V will get charged onto C1 and the output from the op-amp will be a buffered 3V - isn't this what you want?

If you do need a gain of two then restore R4 but take it down to GND/0V - this time, with 3V being sampled it'll be 6V at the output. If your maximum input voltage is 4V you'll get 8.8V on the output - except the LF353 is a poor choice these days - it's not rail-to-rail which means you might see 7.5V maximum on the output - it's going to limit to about 1.5V below the 9V supply voltage.

If, in fact you have a 12V rail, then using it as a gain of two is fine because if your input is restricted to 5V it'll produce a 10V output no problem.

Whoever told you that was mistaken. The papers you cite are talking about "latched comparators" that are specifically designed to have internal storage of their state. These are specifically designed to support ADCs.

The reason most ADCs require sample-and-hold circuits is that they require a certain amount of time to make a conversion, and the analog sample must remain stable for that period of time, or else the output bits will be inconsistent.

Flash ADCs (at least theoretically) take zero time to make a converstion, or put another way, they are converting continuously. If all of the comparators had precisely the same delay, and you didn't have to worry about metastability, you could capture their outputs at any time and directly convert the results to a binary number.

In practice, you do need to worry about metastability, since the comparator outputs can change at any time, and the digital logic that follows has a clock associated with it. Also, the comparators do not all have the same delay. So, either a short sample-and-hold circuit is used ahead of the comparators, or else two-stage synchronization along with an error-tolerant form of thermometer-to-binary conversion logic is used at their outputs.