Problem background: My ultimate aim is to implement a SATA host controller on an Artix 7 FPGA. Having said that I am first focusing on the physical layer. Through my research I have found and read through open source IP located here: http://www.ecs.umass.edu/ece/tessier/rcg/virtex4-sata/sata_core.html
The IP described above is for an older family of FPGA devices and hence cannot be easily imported into the newer Vivado environment.
My question: Would it be better to start the physical layer from scratch using the 7-series transceiver wizard OR should I try to migrate bit by bit the old protocol to be used on the newer device?
- Rocket IO transceivers are not supported in Vivado
- The new device does not have a SATA output port itself like the ML405 board used for the open source core
- From the product guide it seems like the 7-series transceiver wizard handles all the SATA physical layer things such as OOB, 8b/10b, comma detection etc. BUT there is no formal documentation or example design I can locate about SATA.