Electronic – Schematic Critique: Phy interface with RJ45/Magnetics

ethernetphyschematics

I'm working on my first major schematic design and would really appreciate some feedback on the analog side of the 1000BASE-T Ethernet interface. I'm mostly concerned about the analog line termination and the isolated supply of the analog signals and separate ground plane.
This is the analog side. I've used the same center-tap voltage as the phy analog in, and isolated the gnd using a ferrite-core inductor.

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Here's the analog power into the PHY (enough decoupling caps? I used as many caps as input power pins):

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I'm a bit concerned about the fact that the phy (88e1111) doesn't have a dedicated analog GND, so I would assume that the analog outs are relative to the global gnd. Doesn't this mess up my ground isolation external to the device?

I would also appreciate it if you could critique my schematic layout, a client is going to see this and I want it to be perfect!

Best Answer

  1. Where is the transformer? How exactly the termination is done, and what impedance it needs to be is a function of the PHY's requirements, which then dictate a particular transformer configuration. Since the transformer is integral to termination, we need to see it. You should really show everything from the PHY all the way to the RJ-45 jack.

    Your terminations look correct assuming this PHY requires transformers with 1:1 ratio.

  2. Do you really need to terminate all 4 pairs? Ethernet data is carried on RJ-45 pins 1,2 and 3,6. The other two pair aren't used for data but could be used for POE. If you intend to use POE then you definitely don't want the 100 Ω between pairs. If not, just leave them floating. Why are they connected to the PHY at all? Exactly what type of ethernet are you implementing here?
  3. I really don't like disconnecting the PHY ground and main ground with a inductor, as you do with L9. I can understand you want to keep the PHY's high frequency power/ground current off the main ground plane. It looks like you have isolated the PHY's power nicely with L10 and bypass caps C69-C74. All you need to do is connect all the PHY grounds together, then make sure that net has exactly one connection to the main ground. That keeps the nasty high frequency loop currents local, but still gives the PHY the same 0V reference as the rest of the board. With the inductor separating the grounds, the PHY essentially won't have the same 0V reference as the rest of the circuit at high frequencies. That's not what you want.
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