Electronic – Schematic representation of AGND and DGND in a shared ground plane design

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I've seen many questions asking how to connect AGND and DGND in a schematic, and the usual answer is to use some kind of net tie component with a physical footprint (and to approve the resulting overlap DRC violation). While rather hacky, this seems fine for a star- or segregated-ground design with a single point connection.

However, this doesn't really help in a "shared" ground plane design, in which there's no single point of connection between distinct ground planes, and instead relies on the physical distribution of devices and traces to keep AGND and DGND return paths apart in a single undifferentiated ground plane.

My question is, is there a way to represent this in the schematic, other than using a single undifferentiated GND net and relying on e.g. ad hoc annotations, separate sheets, etc to identify the distinct placement/routing domains?

I'm asking specifically about Eagle, but it would also be interesting to know what kind of support higher-end tools provide in this regard.

EDIT: To clarify, I'm specifically asking about a design that follows the principles laid out for example in this article by Henry Ott.

Best Answer

Re-reading that Henry Ott piece, which is excellent and which I have read before, he is saying that there should only be one ground plane and that digital noise isolation should be achieved by placement and routing. I have not yet seen a schematic entry tool that provides a good way to document that sort of thing. Even though a lot of thought and design goes into a placement to satisfy the requirements laid out by Ott, it doesn't look very different at a glance from any other board with a monolithic ground plane and net.

For me personally, if I were reviewing a schematic for a board like that, I would not want there to be multiple net aliases assigned to ground. That is just confusing. I would prefer the schematic to use a single GND net and net name. This could be a matter of preference, so keep that in mind.

Some companies may have guidelines for how that information should be recorded in the schematic. When I worked at motorola 20 years ago (Motorola Computer Group... single-board CompacktPCI computers), the EE's would write a routing requirements document totally separate from the schematic. The layout engineer would use it as a reference for stackup, placement etc. Information about any power plane splits or fills or special treatment for DC-DC converters and controlled impedance traces all would be in the document.

The placement would be reviewed and approved before tracks were placed to avoid unnecessary work. Nowadays, depending on the tool chain being used, many properties can be controlled from the schematic (such as diff pairs, length matching etc). I think that is a better way to do it. But as far as I know, there is not a way to convey the complex placement constraints required to follow Ott's recommendations. If you feel there is a need, you can attempt to institute a standard operating procedure at your company to help document that kind of thing in a standard way. Sometimes bosses appreciate that sort of thing. But it may not make sense for very small companies that don't do designs often.

Another thing I have occasionally seen is a floor-plan diagram. This is often drawn with some type of block diagram tool and is not highly accurate dimensionally speaking, but does provide a an indication of the relative locations of key components. This could be a separate document or could be added to the schematic on page 2 or page 3.

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