I'm studying a Phase Locked Loop used for FM demodulation, obviously a phase detector is used in the system.
A basic implementation of a phase detector is a multiplier followed by a lowpass filter. I am a bit confused on how to select the cutoff frequency of this lowpass filter.
I know that the multiplication of the two signals will produce two signal components:
1) A component where the carrier frequency has been doubled.
2) A component where the carrier frequency has been eliminated. This produces a "phase error" component.
I know that the purpose of the lowpass filter is to isolate the "phase error" component but I am confused at what frequencies the "phase error" contains.
I'll setup an example with relatively simple numbers to illustrate my confusion:
Carrier Frequency : 1MHz
Peak Frequency Deviation : 75kHz (I believe this is common for U.S. radio stations?)
Max Frequency of Original Unmodulated Message : 25kHz
FM Modulation Transmission Bandwidth : Carsons Rule: 2*(peak frequency deviation) + 2*(Max message frequency) = 200kHz
This would mean that the incoming modulated signal would have a frequency range from 800kHz to 1200kHz. This means that after the multiplier in the phase detector, the double frequency component would change to a range of 1600kHz to 2400kHz. In this case, would I select the cutoff frequency of the lowpass filter to be below 1600kHz so as to eliminate these higher frequencies?
Or is it that without the carrier frequency, the remaining frequencies are centered around 200kHz so that the "phase error" component contains frequencies from 0Hz to 400kHz? This would be because the frequency needs to be able to deviate 200kHz +- from the center point as this is the transmission bandwidth? In this case the cutoff frequency would be ~400kHz.
Or at this point in the phase locked loop, would the message already be demodulated so that the maximum cutoff frequency would be near 25kHz?
I suppose my confusion is rooted in what frequencies remain in the "phase error" component that has the carrier frequency removed.
edit:
So I'm still a bit confused on the lowpass behavior of the loop as referred to in an answer below. I understand that the integrator has a laplace transformation of 1/s but when I actually find the loop transfer function it appears to have high pass behavior instead. Below is a photo of what I mean.
To me this looks like a high pass behavior?
edit2:
Confusion lied in that I was viewing the system from an output/input relationship rather than an input/output relationship in which the lowpass behavior is indeed present.
Best Answer
When building a phase locked loop, the purpose of the low pass filter is poorly understood.
When you wrap a phase feedback loop around a VCO, the integration of frequency to phase causes a 20dB per decade fall in open loop gain with frequency. It's this falling gain that gives you an unavoidable low pass behaviour for the phase locked loop as a whole. You can choose the bandwidth where the loop gain passes through unity by choosing the loop gain. At modulation frequencies below the loop bandwidth, the PLL output follows the input, at modulation frequencies above it rejects them.
Notice I've not yet mentioned any low pass filter. It's not needed for operation. It's not needed for stability. It is needed however, to get higher performance, better following of the input within the loop bandwidth, better rejection of the input and of the doubled PSD output outside the loop bandwidth.
The loop filter is best designed as something you add on, after you've designed a working stable loop of the right bandwidth. It must have unity gain at the loop bandwidth, or it will change the loop bandwidth. It must have low phase shift, much less than 90 degrees, in the few octaves around the loop bandwidth, or it will make the PLL unstable.
With that introduction, your PSD and filter...
If you want to demodulate FM modulation to 25kHz, then your PLL loop bandwidth must be significantly more than this, say 50kHz. Given your VCO and PSD gains, choose an amplifier gain in your loop to get unity gain at 50kHz.
If you want your resulting loop to be stable, then any phase shift from a low pass filter must be small at 50kHz. If you only use a single pole lowpass filter, then a 100kHz break frequency gives you about 30 degrees phase shift at 50kHz, even a 50kHz break would give you 45 degrees. Beware going too close to the loop bandwidth. All circuits have extra lowpass poles from finite opamp GBW, stray capacitances etc, which will increase the phase shift at high frequencies. You must still be well clear of 90 degrees when all these unwanted extras are added to your explicit lowpass filter.
If you use a type 2 loop, with an extra integrator at low frequency, then you should push the breaks further away, with a lowpass break at 160kHz, and a broken integrator break at 16kHz, a decade in frequency between them, geometrically centred on your loop bandwidth.
You can use higher than first order for the lowpass filter. The main criteria are that it should reject the doubled output from the PSD, while still having << 90 degrees phase shift at your loop bandwidth. It would be as well to reject the fundamental 1MHz at the PSD as well, real PSD's won't have infinite rejection of it. This means a higher order 500kHz would be reasonable. Do a design and use a simulator to check phase shift at the loop bandwidth.
You'll recognise that this isn't the way we're usually taught to design PLLs. You start with the loop filter in place, and place it so that the damping factor is right. However, my design method tells you more about the fundamentals. And if the phase shift from the loop filter is much less than 90 degrees, say in the 30-50 degree region, the damping factor will be reasonable. Nobody fields a PLL without testing it, and during the testing you have the opportunity to tweak the damping while observing its transient behaviour. Bear in mind that many RF VCOs have a volts-to-frequency gain that varies by 2:1, even 3:1, over their range, which changes the loop gain, and so bandwidth, and so damping. PLL design becomes a compromise between stability and transient behaviour over the range, going in from damping direction is not going to help you. Interestingly the type 2 loop, because the phase shift from the integrator flattens the phase shift curve from the low pass filter, results in a smaller change of damping factor with varying VCO gain than a type 1 loop. Now who would have spotted that from damping factor equations?