I've worked with DDR2 and DDR3 memories and usually stuck to 50 ohm impedance for traces. But i do see that SoCs and DDR2/3 memories seem to support other impedances such as 30, 60 and 150 ohms.
Now if using other impedances allows for a cheaper layer stackup then i guess i should have the option of going for it as long as i'm willing to accept the downsides of higher or lower impedances regarding EMC suspectibility and radiation.
Are there any other specific downsides to this ?
Best Answer
There are no real downsides to any impedance for EMI, as long as you have matched impedances on source, termination and trace.
One thing that many fail to consider is the typical routing of DDR2/3 with a data line that goes far enough from the CPU to be considered a transmission line, then T's to go to each chip (or 4 chips, etc.) The 50 ohm impedance just dropped to 25 ohm, with two traces in parallel. This creates an impedance mismatch, which always creates a reflected signal and noise on the line.
The proper way to handle this is to T the lines either close enough to the CPU to still be considered a lumped length, with a series termination at the T of 1/2 the line impedance. The signal sees 25 ohm resistor to a 25 ohm parallel set of 50 ohm transmission lines and everything is good. Or this can be done where the T's will be short enough to be considered lumped at the two RAM chips.
A similar setup can be used to match impedances differing CPU to RAM, but it is best to keep SoC and RAM source and termination impedances the same, then make traces to match.
If you have differing impedance only at the RAM side, you should be able to use parallel or series termination resistors to match to that.