Electronic – Separating ground planes in PCBs

The layout you showed looks like what's called copper-backed coplanar waveguide (CBCPW). That means the ground return for the waveguide is not just in the coplanar grounds (the ground fills on the same layer as the signal traces) but also in the plane layer immediately "below" the signal layer. This structure is fairly esoteric, in the sense that I've only seen it used in digital systems when data rates exceed 20 Gb/s.

I found what looks like a reasonable discussion on the differences between CBCPW and microstrip in a Microwave Journal article by Rogers Corp engineers.

This article shows that the CBCPW has lower loss than microstrip at frequencies where radiation loss becomes important in the microstrip, roughly from 25 GHz and up, which explains why CBCPW is not widely used at lower frequencies.

Addressing your question, the article points out some special requirements for grounding vias in CBCPW structures:

For proper grounding, CBCPW circuits employ vias to connect the top-layer coplanar ground planes and the bottom-layer ground plane. The placement of these vias can be critical for achieving the desired impedance and loss characteristics, as well as for suppressing parasitic wave modes.

This basically means that without frequent stitching vias between the coplanar ground and the backing ground, power could be transferred to undesired propagation modes, which would cause either excess insertion loss or strong dispersion in the transmission line characteristics.

It is a pretty low parts count design, but it is by no means simple. It helps to understand how the chip works inside to see what pins are more sensitive to stray EMI than others before doing a layout. Then you can determine where coupling to ground is useful and when it can interfere. ( This is just learning curve info not specific to your layout) Although many students use the physical layout approach, it defies logic and when you want to understand how it works, you need to use logic in your schematics not just physical layout. This is most useful when it doesn't work.

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When you discover the load regulation is poor due to the layout of the external transformer in relation to RFB feedback, which schematic will you follow and how will you discover why it fails in your layout. Unfortunately what schematics do not show is the equivalent circuit of a ground plane and its coupling. This is why a more "Logical" schematic is important and rules for small inductive loops is important and coupling to ground planes. Although I concur with your aadvice given, this design will be very noisy and suffer in regulation becuase of how the boundary mode processing works inside the chip. A more reliable design will use large voltage feedback thru a tertiary winding (which they use in msome aqpplications)

It may work, but how well is the question.

EMI radiation, Load regulation, Step response and ripple are important measures of performance which are affected by this clever chip's internal processing of the current waveform using the MOSFET resistance. When it fails you can try to understand how it works. With your schematic, all you can do is see that the parts are connected to the right pin.

These basics although may seem tedius to you, they are critical to getting the perfromance offered by the chip. Layout is critical in this design because of the simplified external feedback of transient switching. I would use a small planar SMD torroidal transformer such as the one used by Linear Technology and follow their layout guidelines.