Electronic – Serial adder using one’s complement arithmetic

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The Apollo Guidance Computer (AGC) used one's complement arithmetic. The following clip from Frank O'Brien's book on the Apollo Guidance Computer (2010) offers a partial justification for this engineering decision:

Key to the simplicity of such adders is the requirement that numbers
employ one's complement for their representation.

Question:
Why is one's complement representation key to the simplicity of a serial adder?

Here is the clip in context from The Apollo Guidance Computer: Architecture and Operation (http://amzn.to/2EfVFla):

Best Answer

Brian's comment is the obvious one, I think -- the added idea of "+1" being required for two's complement notation. (I upped his comment.) The implication being here that there would have to be significantly more logic to perform this added function which one's complement doesn't require.

But I don't think that was it.

A serial adder performs exactly the same functions, whether one's complement or two's complement. The only difference is that the carry-in for two's complement starts as "1" instead of "0" for negative numbers, while the starting carry-in for one's complement is always "0," regardless. This isn't a problem, though. For a two's complement serial adder, it's just a matter of adding a "preset" to the carry-state FF (in addition to the "reset".) And that's actually not all that difficult. It does add something. But I just don't think it adds enough to make a strong case this was why.

(If you want to see the typical more modern "serial adder" approach, take a look at Use of D flip-flop in Serial Adder. There you can see that FF I'm talking about, above.)

Negative numbers in either notation use a "1" as the sign bit. This is used to invert the bits (if appropriate) as they are shifted through the adder. This also would be identical in both cases. Zero additional logic on this point.

So the reality, I think, is a little different. It's about the possibility of completely removing the FF, entirely. They simply used an OR gate followed by a delay line circuit between two half-adders in order to entirely replace the need for a FF. This OR gate plus delay line has significantly fewer parts than a FF and it won't support "preset" easily.

Here's a quick diagram:

I can't find documentation on this as being the actual reason. If I could, I'd post it here. But I do recall the use of delay lines "back in the day" for these and upon reflection I suspect the difference between a simple gate + delay line vs the alternate use of a full FF (as modern books on the topic would seem to have it done) was more likely the reason, in my opinion.

+1 for your question, by the way. You made me think a moment and I appreciate that.

Related Solutions

4 bit subtractor using 2’s complement of an adder

RYour expressions for individual bits shouldn't use the term "B+1", that can have three possible values (0,1,2) and require two bits to express.

Your expressions for all 4 bits of the adder should be the same:

Sn = An^~Bn^Cin; Coutn = (An&~Bn)|(Cin&(An^~Bn));

Where 'n' represents the bit number.

The Cin for the entire adder should be set to a 1 to do the complement + 1 function.

Try this approach to thinking about it:

Forget about A for the moment. How would you create the 2's complement of B with your logic?

You would put the complement of B into the 4 input lines of the adder, then to add the 1 you would set the carry in. This should result in the 2's complement of B at the output.

Now add A into the other 4 input pins. You should get the A-B at the output. The carry output is then used as an overflow status bit that tells you about the relative magnitude of the two operands.

Electronic – Serial Adder vhdl design

z : out std_logic_vector(n - 1 downto 0)); The output must be std_logic, because it is a serial output

Also, you can use the + operator directly to the std_logic_vectors. Just add the "ieee.std_logic_signed" library So that you can write z_reg <= x+y;

if rising_edge(clk) then if clr = '1' then --clear all the registers, and flip flop

            c_reg <= '0';
            z_reg <= (others => '0');
        elsif load = '1' then
            z_reg <= x + y;

        else --execute sum       

            --full adder logic      
            z <=  z_reg(0);
            z_reg <= '0'& z_reg(n-1 downto 1);
        end if;
    end if;

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Related Solutions

4 bit subtractor using 2’s complement of an adder

Electronic – Serial Adder vhdl design

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