Electronic – shift registers: differences between the standard parallel-in serial-out ICs


I must be blind… I'm trying to decide which of the '165, '166, and '597 shift registers is appropriate/inappropriate for a SPI input shift register. All are 8-bit parallel in.

It looks like the HC165 has a latching asynchronous load input (parallel load triggered by a pulse), the HC166 has a clocked synchronous load input (parallel load triggered by the same clock edge as the serial shift, when load enable is asserted), and the 597 has a separate set of load registers.

Can anyone add anything to the differences, or suggest which might be the most appropriate for SPI? (my gut call is the HC165, with the parallel load triggered by the inverted SPI CS line, and I'd have to add a 1-gate tristate driver for the MOSI signal)

Best Answer

The 74xx165 is the more typical choice. The 74HC597 is only better if it will be necessary to sample the input during a byte transition (and then make the sample available for the following transmission). Because the front-edge latch is rising-edge sensitive but the parallel-load latch is level sensitive, there will often not be any good signal anywhere to clock the parallel-load latch. The part would be much nicer if either both latches were level-sensitive, but otherwise the front-end latch is more likely to be a nuisance than to serve any functional purpose.

BTW, the similar timing issues exist with the 74HC595's asynchronous clear. If the parallel-load pin were level-sensitive, one could asynchronously drive the clear pin and the parallel load, so as to force all outputs to a known state. Unfortunately, the edge-triggered parallel-load pin gets in the way of such a design; one could asynchronously drive the clear pin, but one would have to then drive the parallel-load pin some time after the clear signal had registered.