PCIe Golden Finger – Should Gold Tips Be on Top and Bottom Copper Layers?

I'm late to the game, but I'll give it a shot:

1- It appears that for a lot of manufacturing houses, 105 microns is as high as its gets. Is that correct or are higher thickness possible?

Some fab shops can plate up internal layers. The tradeoff is usually larger tolerance in the overall thickness of the board, e.g. 20% instead of 10%, higher cost, and later ship dates.

2- Can the copper in the inner layers be as thick as the copper at the top and bottom of the board?

Yes, though inner layers do not dissipate heat as well as outer layers, and if you're using impedance control, they are more likely to be striplines than microstrips (i.e. using two reference planes instead of one). Striplines are harder to get a target impedance; microstrips on the outer layers can just be plated up until impedance is close enough, but you can't do that with internal layers after the layers are laminated together.

3- If I'm pushing current through several board layers, is it necessary or preferred (or even possible?) to distribute the current as equally as possible throughout the layers?

Yes, it is preferred, but it is also difficult. Usually this is only done with the ground planes, by way of stitching vias and mandating that holes and vias connect to all planes of the same net.

4- About the IPC rules regarding trace widths: Do they hold up in real life? For 30 Amps and a 10 degrees temperature rise, if I'm reading the graphs correctly, I need about 11mms of trace width on the top or bottom layer.

The new IPC standard on current capacity (IPC-2152) holds up well in real life. However, never forget that the standard does not account for nearby traces also generating comparable amounts of heat. Finally, be sure to check voltage drops on your traces as well to make sure they are acceptable.

Also, the standard does not account for increased resistance due to skin effect for high-frequency (e.g. switching power loop) circuits. Skin depth for 1 MHz is about the thickness of 2 oz. (70 µm) copper. 10 MHz is less than 1/2 oz. copper. Both sides of the copper are only used if return currents are flowing in parallel layers on both sides of the layer in question, which is usually not the case. In other words, current prefers the side facing the path of the corresponding return current (usually a ground plane).

5- When connecting multiple layers of high current traces, what's the better practice: Placing an array or grid of vias close to the current source, or placing the vias throughout the high current trace?

It's best (and usually easier from a practical point of view) to spread the stitching vias out. Also, there is an important thing to keep in mind: mutual inductance. If you place vias that carry current flowing in the same direction too close to each other, there will be mutual inductance between them, increasing the total inductance of the vias (possibly making a 4x4 grid of vias look like a 2x2 or 1x2 at decoupling capacitor frequencies). The rule of thumb is to keep these vias at least one board thickness from each other (easier) or at least twice the distance between the planes the vias are connecting (more math).

Finally, it is still wise to keep the board's layer stackup symmetric to prevent board warpage. Some fab shops may be willing to go to the extra effort to fight the warpage from an asymmetric stackup, usually by increasing lead times and cost since they have to take a couple tries at it to get it right for your stackup.

I'm assuming you're after a thicker plating on the mating portion of the PCIE connector.

A gerber file, regardless of extension, is not capable of showing details like this. A gerber file contains a sequence of commands that describe the two dimensional geometry of a single layer of a PCB. The geometry is made up of all of the lines, arcs, and shapes, all with coordinates, that when taken together show all of the positive or negative space on the board. Could be copper, solder mask, silkscreen, solder paste, etc. Things like layer-to-layer spacing, hole plating, board material, plating thickness etc. are beyond the scope of a gerber file.

Furthermore (although less relevant and more pedantic) the use of extensions like .GTL to differentiate between layers is not part of the gerber standard. Section 2.1 of the standard states that The standard extension is “.gbr” or “.GBR”. Furthermore, section 6.2 of the specification "Most common bad practices" recommend against using non standard extensions, although this particular use is generally well understood by board houses. Still, when you submit the gerbers you're generally required to specify what layer each gerber represents. The board house will build the board based on your answer, not the extension of the individual gerber files.

Therefore:

1. It is not possible to represent this using a gerber file
2. Even if it were possible, you wouldn't use the file extension to do it.

Gerber files are allowed to contain comments, so you could write something in there like "Manufacture this layer with a 2oz plating" but even if you did, it's unlikely that another human being would ever read the comment.

Not very helpful so far, eh?

In order to get a special plating, you'll likely need to enlist the services of a full-service board house. In addition to the gerber files, you'll deliver a drawing of the board (usually a PDF). Somewhere in that drawing there will be text or pictures that tell the board house some additional information like:

1. Which layers of the board are represented by which gerber files
2. What order the layers go in in the board stack-up
3. The material that the board is made of
4. The thickness of the board
5. Any non-standard features of the board - In your case, you probably need to specify a different plating for the edge connector than the rest of the board. This would probably be done by circling the area on the drawing, and writing some text specifying the plating.

The board house will have a real human being look at the drawing - possibly offering feedback depending on their capabilities and a quote to manufactuer the board. Express shops are much more streamlined. By standardizing the process and increasing the use of automation they are able to offer boards at lower prices than a full service shop.

There's a small possibility that the board house would want a gerber file with only the geometry to be special plated so that they could generate the correct mask. In that case, you would include a gerber with only the PCIE contacts and specify to the board house what that particular file contains.