I highly recommend the first thing you do is purchase High Speed Digital Design: A Handbook of Black Magic. Read it twice, then read it again :)
One important point. The crystal frequency doesn't matter here, you need to know the speed of the signals on the lines in question (which can be many times the crystal frequency). More over its actually rise / fall times that drive almost all signal integrity issues, not the digital frequency of the signal.
Designing for DDR isn't really that simple. High speed design can be a bit of a 'voodoo' art, even if you have $10,000+ simulation software. In other words, don't expect to nail the design the first time without putting in the work to understand the issues involved, a check list really won't cut it.
What I mean is, you really should start by reading the book I linked. It will give you enough background that the information in AN2582 will make sense (side note you linked the wrong pdf in the op). It will also allow you to understand the design trade offs you'll likely have to make when laying out the PCB.
That being said, here are my thoughts:
Routing Guidelines:
High level things to consider / avoid:
1) Route on a single layer, with a solid ground plane under it. Avoid vias like the plague. If this isn't possible, the DQ and ADDR groups are most critical, route those first, try to only move signals as groups to different layers.
2) Make sure you impedance match the traces: 50-60ohms, whatever comes out to the 'nicest' trace width for the design. Note the difference between differential and single ended lines and match the impedance appropriately.
3) Maintain proper signal spacing (i think 3*signal line width is preferred). This will help limit crosstalk between signals.
4) Match trace length of all related signals / groups (differential pairs, data bus, address bus, etc). Try to keep all traces to roughly the same length, that is you don't want the address group to be 1cm longer than the data group if you can avoid it.
5) Use source termination. You probably don't need parallel termination nor a Vtt given your board size and use of a single ram ic.
6) Pay special attention to Vref, it needs to be stable: well decoupled, fat traces. For a single ram module you can generate it with a simple resistor divider.
7) Don't use resistor banks for the termination, use individual resistors.
8) Expect that you'll need to 'play' with the source termination resistor values on the first prototype. Basically put a scope on the signal and try various values in the region of (trace_impedance - driver output impedance) = R. Look for the value that results in the cleanest signal (read up on eye patterns).
Signal Groups:
They are (NOTE: Taken from AN2910 and this is for a 64bit + 8bit ECC module, you don't have all these pins):
Data Group: \$MDQS(8:0), \overline{MDQS}(8:0), MDM(8:0), MDQ(63:0), MECC(7:0)\$
Address/CMD Group: \$MBA(2:0), MA(15:0), \overline{MRAS}, \overline{MCAS}, \overline{MWE}\$
Control Group: \$\overline{MCS}(3:0), MCKE(3:0), MODT(3:0)\$
Clock Group: \$MCK(5:0)\$ and \$\overline{MCK}(5:0)\$
Stack Up:
There are lots of ways to do this. Micron gives their recommendation for 6 layer stack ups with 3 or 4 signal layers in app note TN-46-14.
Really stack up is an entire topic of its own, but if your device has the 'standard' assortment of devices on it, these recommendations should work fine.
Other Stuff:
I think the rest of your questions are answered in the linked pdfs or AN2582. There is another checklist available in AN2910.
Good questions.
1) Does REF_CLK must be routed without vias.
Whenever you see something like "must be routed without vias" without a good explanation, chances are that someone does not fully understand what is going on and just think that is a good idea.
One of several things may be the issue:
- Different trace impedance on different layers, which will cause reflections whenever there is a via.
- Reference plane problem, because the impedance between the power planes of the design is not low enough.
Both of these are easy to avoid and is good practice - often even required if you want to pass EMI tests, build a solid design etc.
So provided you do this, you can use vias without any issues. The faster the signals, the more careful you have to design the vias. I have previously written about how to design vias for 28+ GBps signals here.
2) Does REF_CLK need termination resistor?
Best thing to do here is a quick simulation with your favorite IBIS simulator - or have someone do that for you (sorry, these tools costs money - but are worth it).
If you have very fast edge rates, chances are you need a termination resistor if the trace is electrically longer than about 1/3 of the rise/fall time. Use simulation to be sure (unfortunately you did not provide enough information about your design, or I might just have done it right away).
3) Is 4mm difference in trace length @50Mhz acceptable?
Another good question. Look at the rise/fall times of your signal. If the electrical length of the rise/fall time is significantly longer than the trace length mismatch, this will work just fine. Actually it is a good practice not to overconstrain layouts, even though it is often possible to match trace lenghts within a very narrow tolerance.
Best Answer
Faster rise time is just another way to refer to a high frequency. The higher the rise time the more "squared" a signal is, and a square signal is nothing else but the sum of many sine signals of increasing frequency (the more components of high frequency, the more "squared" the signal will appear)
As frequency rises, the impedance that comes from inductances (PCB traces for instance) also rise. Other things to take into account for high speed PCB design: