The basic formula for a capacitor is: -
Q = \$C\cdot V\$ and this can be differentiated to \$\dfrac{dQ}{dt} = C\cdot\dfrac{dV}{dt}\$
rate of change of charge, \$\dfrac{dQ}{dt}\$, is current therefore: -
I = \$C\cdot\dfrac{dV}{dt}\$
Power\$^1\$ is I (current) x V (volts) therefore power taken by a capacitor is \$C\cdot V\dfrac{dV}{dt}\$.
But V multiplied by its differential will always average to zero therefore a capacitor doesn't get warm theoretically. However, due to losses in the capacitor (seen as either an equivalent series resistor or parallel resistor), it will get warm if pushed hard enough.
This is usually due to dielectric losses or the effective series resistance (ESR) of the capacitor.
If the current is 25mA and the power source is 50 or 60Hz then the capacitor is unlikely to get measurably warm.
\$^1\$ If you integrate this formula with respect to time, power becomes energy and you get the hopefully recognizable formula seen below: -
\$E = \dfrac{C\cdot V^2}{2}\$
So you could fill a book with the answer to this question, in fact I think I have some on my shelf
Let’s run through your questions.
Should you use a 4 layer board instead of a 2 layer? I say absolutely yes, the cost argument to going 2 layer is a weak one at best compared to the advantages. Obviously it can be done, and is done, and in this devices case I see they placed VCC and GND right next to each other to make this easier to accomplish. So while I would go 4 layer, you can probably get away with 2 if you want.
Why decouple?
Now without going too deep consider the goal of decoupling your processor. You are trying to supply a stable voltage to it despite the fact that it has dynamic current demands. When your processor is active for instance and its transistors switch they are requesting more current. This current is a change, an increase to the current draw at steady state. Now you have a changing current but where are you going to get that current from?
Well first there’s a little decoupling on the die, but then it tries to pull it through the package power and gnd pins. It wants to get at that capacitor you placed outside of your device but before it gets there it has to travel through the bond wires and or package substrate, out the pins, and down your traces. All of this contributes to the inductance, and ultimately the impedance of the path from the die inside the chip to the capacitor.
Why does this matter? Well because an inductor “resists” changes in current consequently its impedance increases as frequency increases. That’s a simplification, but what happens when you try to drag that change in current through your package and routing is that the inductance limits the amount of current you can get.
So your goal when placing your decoupling capacitors should always be to minimize the impedance, and thus the inductance from the pin to your cap. Now with a QFP package like this you may find the shortest possible connection is right at the pins, with a 4 layer board and a BGA it might be directly underneath, but in practice you can achieve even lower impedance on top layers as well.
Don’t ignore GND either. Current flows in a loop, it does you no good to have a super short path to VCC and long winding path to GND. So if you’re going 2 layer I would put the caps parallel, as close as possible to GND and VCC, route directly to the pins, and then bring power and gnd into the caps. Your goal is to minimize the loop size.
More 4 layer arguments and selection
The goal of what we call Power distribution network design is to minimize the impedance across the range of frequencies that your chip will request. To that end having a nice fat GND and VCC plane leading from your caps/part to your regulator will be a much lower impedance path for your lower frequency down to DC. Short of that fat wide traces are recommended if you can.
Cap selection
For this processor and your board I think 0.1uF 402s and 0805 10uF are a good choice. The smaller package size helps you have a smaller loop size. I can do 201 by hand, never bought a 1005, but it is easier with a microscope. For more complex designs we select a range of decoupling capacitors to cover the range of frequencies that the part might demand from us. Blindly doing this as in just using 0.1uF, 0.01uF, and 0.001uF as is often suggested can lead to nasty anti resonance peaks giving you high impedance and certain frequencies Again this is a simplification, but I don’t think digging into that here will help you. Interesting to note that placing the 10uF capacitors further away is ok as their role in this design is for the lower frequencies where the impedance caused by the trace inductance will be lower. Also the frequency range you can effectively decouple to is limited by the impedance of the package we discussed earlier.
Actual part selection
There are tons of capacitors out there, and usually we don’t make specific part recommendations. But I would look for a 402 0.1uF ceramic capacitor with maybe an X7R temperature coefficient, and a voltage rating double your VCC. Here’s an example of one I have on a BOM
Your questions
OK long winded response I guess but sometimes if you get why something is done it makes it easier to decide how to do it.
So you say:
2 layer board: Seems ok for this, I always prefer a 4 as explained above. There are other benefits such as controlled impedance of traces, less noise, easier to pass emi. I don’t know what your board will do but without reference planes your traces return current will be forced to all follow whatever GND wires it can find. Gets a little messy.
GND pours: Meh it will help balance the copper on top and bottom layers for etching and re-flow, but really you’ll carve it up so much with traces it won’t do you that much good. Better to concentrate on getting power to that chip with as low an impedance as possible. Maybe you can figure out how to run VCC and GND as two copper pours?
Components on top: OK doesn’t really matter, in this case better to have decoupling on top than to go through vias to the bottom. If you are hand assembling it doesn’t really matter, but it would be cheaper to manufacture.
Traces on top and bottom: Definitely you probably won’t get away without this.
Decoupling: I talked about this at length.
Ah what else oh the ferrite, I didn’t see that in the app note. I’m assuming maybe it’s used to isolate one of the more sensitive VCC pins, maybe a PLL or an ADC. And it actually goes VCC supply -> Ferrite -> VCC Pin, with the cap from VCC pin to GND? If so that makes sense it’s probably just a little filter.
Got any questions? Just ask, it's hard to put everything you need to know about decoupling in one answer but hopefully this helps.
Best Answer
Subset summary:
I = excess current to be provided.
T = time to provide this extra current.
V = acceptable drop in voltage during this period.
C = capacitance in Farad to meet this requirement.
Then:
In theory, and close enough to be useful in real applications:
One Farad will drop in voltage by one volt in one second with a 1 Ampere load.
Scale as required.
The results are not encouraging :-(.
(1) Providing a capacitor to do everything
For over current of I ampere, droop of V volt over time T seconds (or part thereof) Capacitor C required is, as above)
C = I x T / V <- Cap for given VIT
ie more current requires more capacitance.
More holdup time requires bigger capacitance.
More acceptable Voltage droop = less capacitance.
or droop given CIT is, simply rearranging
or time a Cap C will hold up given C I V, simply rearranging =
So eg for 1 amp overload for 1 second and 2 volt droop
C = I x T / V = 1 x 1 x/2 = 0.5 Farad = Um.
Supercaps may save you as long as required peak current can be supported.
SUPERCAP SOLUTION
A Supercap (SC) solution looks almost viable.
These 3F, 2.5V supercaps are availale ex stock from Digikey for $1.86/10 and under 85 cents in manufacturing volume.Prices
For the 3F, 2.7V unit the acceptable 1 second discharge rate to 1/2 Vrated is 3.3A. Internal resistance is under 80 milliohms allowing about 0.25V drop due to ESR at 3A.
Two in series gives 1.5F and 5.4V Vmax. 3 in series gives 1 Farad, 8.1V Vmax, same 3A discharge and 0.75V drop due to ESR at 3A.
This would work well for surges in the tenths of a secnd range. For the specified wort case 3A, 5 seconds requirement perhaps 15 Farad is needed.
The same family 10F, 2.7V $3/10, 26 milliohm looks good. 10A allowed discharge. Two in series drooping from 5.4 to 5 volts at 3A gives
Getting there.
(2) IF the droop causes system reset etc and one wishes to avoid this (as one usually does :-) ) an often useful solution is to provide a sub supply for the electronics with cap that hold them up over the dropout period.
eg electronics need say 50 mA. Holdup time desired = say 3 seconds (!). Acceptable droop = 2V say.
From above
= 0.075 Farad
= 75,000 uF
= 75 mF (milliFarad)
This is large by most standards but doable. A 100,000 uF supercap is reasonably small. Here the 3 second holdup is "the killer". For a more typical say 0.2S dropout the required cap is
75,000 uF x 0.2/3 = 5000 uF = very doable.
(3) A small holdup battery for the electronics can be useful for obvious reasons.
(4) Boost converter: In a commercial design where 4 x C non rechargeable batteries were used, to provide 5V, 3V3 and motor drive battery (exercise equipment controller) end of life Vbattery got well below needed 5V during end of battery life and much much below when motors operated. (The primary design was not mine). I added a boost converter based on a 74C14 hex Schmitt CMOS inverter package to provide 5V to the electronics at all times plus 3V3 regulated to the microcontroller. Quiescent current of boost converter and 2 x LDO regs and electroncs under 100 uA.
E&OE - may have got something on wrong side somewhere there, easily done. If so, somebody will tell me about it :-).
ADDED:
Query: It has been (quite understandably) suggested that
I am not sure you are answering the users main question.
To stop from overloading a power supply it does not seem feasible.
It is not a case of power supply cutout, it is a case of wanting to allow higher current for short periods(on the order of 5 or more seconds).
This seems like a case of needing another power supply
Response
I believe that I am addressing the question completely, as asked, BUT I am also addressing what I believe is liable to be the larger question as well.
Consequently, there seem to be tangents and irrelevant material here.
I have addressed points unasked as well as points asked based both on my own experiences in closely analogous applications and also on general expectations.
The issues are
"What if demand exceeds supply" and
"What if supply falls below demand".
These are one and the same in practice but may have different causes.
Note that my answer (1) specifically says
and his question was
ie dealing with overcurrent is exactly what he is asking.
BUT overcurrent is caused by overload and, when the "cost" of trying to deal with overcurrent is seen (0.5 Farad caps or whatever) then the perspective may well turn to "what can we do to ride out this overload differently". The next most obvious "solution" is to accept the hit on motor performance, let the supply rail fall BUT maintain a local supply to keep the eectronics sane. Another solution which I didn't bother addresssing is to deloa the system by eg slowing servo rates when all are on at once. Whether this is acceptable depends on the application.
The reason that we can TRY to address the short term overcurrent situation is that the supply has spare capacity most of the time and this is used to charge the caps prior to the surge event. The caps do not magically manufacture extra current, just save up spare current for arainy day.
To supply current the capacitor MUST lose voltage so I specify the acceptable limit for that too. I think you'll find that if you couch his requirement in numbers and then plug them into my formulae that his question as-asked will be answered.
Re on geometrikal post.
What happens depends very much on the original supply characteristics.
Imagine an LM350 was being used. Datasheet here. This is essentially an LM317 on steroids. Good for about 3A in most conditions and 4.5a IN MANY, deep-ending on application. 3A guaranteed. Fig 2 shows that it is good for 4.5A for a Vin-Vout differential of 5 to 15V depending on other issues. It can be run up near its current limit with good regulation. If being run at 3A and if the drop across it is not too high and it is well heatsunk it will not be hot and intermittent peaks of 4.5A will be provided. Do this too often and the temperature will rise and figs 1,4,5 and a few things unshown will affect how it behaves. First off Vout will start to droop on peaks and a capacitor on the output will help it serve the load. Increasing drOop and longer peaks and the capacitor will be called on to do more. If the IC decided to completely cut out for a moment (which it is unlikely to ever do) as long as T x I / C does not exceed the voltage droop which is acceptable the capacitor will do the whole job. Restore Iout to 3A and the capacitor will recharge until next time.