Electronic – SN74HC595N Shift register output bizare

outputregistershift

schematic

^{simulate this circuit – Schematic created using CircuitLab}

I'm using an 8-bit shift register on a very basic application for learning purposes, I have three buttons connected to SER, RCLK & SRCLK pins, OE & SRCLR are LOW, reverse output is empty since I'm only working with one chip, and the 8 outputs are connected to LEDs.

The behavior is kind of unexplainable, I expected that pressing the clock button while the SER button is HIGH/LOW will define the input data, and then the latch button will display the output on the LEDs, but somehow the three buttons have the same behavior, they either turn all the LEDs on or nothing happens.

I know I should probably show what I'm working with, but wires are everywhere and I doubt that would be helpful.

Thank you

Best Answer

Probably your switches are actually normally open (you chose the normally closed switch symbol), also there are a bunch of shorts between Vcc and SER, OUT4 and SW3, for example, that you probably do not intend.

You need pull-down resistors to get predictable logic levels at the chip. Open on an HC logic chip input just means it can float around to some unpredictable state. Try 10K or 4.7K to ground.

schematic

^{simulate this circuit – Schematic created using CircuitLab}

You should have resistors in series with each LED to limit the current. 1K is fine. You should have a bypass capacitor (eg. 100nF) across the chip power supply.

There is a more subtle issue- the mechanical switches "bounce" and you may (or may not) get many clock edges for a single press, so even with the resistors and bypass cap this will probably do strange-looking things, at least some of the time.

Search for debouncing circuits to figure out how to add that. One of the simpler ways, assuming a SPST-NO switch, is to use a Schmitt trigger gate such as the 74HC14.

schematic

^{simulate this circuit}

You only need the debouncing on the CLOCK input, since you will only send a clock pulse when the data input is stable, and since multiple edges on the LATCH input will just transfer the same shift register data again.

Related Solutions

Electronic – How to design a left shift register

One approach is to design the circuit as a regular two bit binary counter using a pair of flip-flops. Then you put some circuitry on the outputs that decodes the four counter states into the output sequence that you desire. Such decode functions actually already exist as standalone chips.

Here is the state table related to this:

Binary 00 -> Decode 0001

Binary 01 -> Decode 0010

Binary 10 -> Decode 0100

Binary 11 -> Decode 1000

Binary 00 -> Decode 0001

.....

[and so on]

There are other ways to make your recirculating shift register but they often have the problem of getting unwanted states in to the output stream such that more than one bit would be set at a time. The binary counter followed by decoder does not have that problem.

You may find it interesting to know that there is a commonly available chip that performs the counter and decoder operation all in one IC chip. The CD74HC4017 is one that does this with 10 output pins.

Electronic – FPGA design rules – Using a Module Output Register Value Internaly

Seems fine.

Three suggestions/recommendations:

Use non-blocking assignments for registers
Use an if-else instead of the case.
You are missing the reset clause - how does it know what value to take when in reset.

So the code would become:

always @ (posedge clk) begin
    if (rst) begin
        Busy <= 1'b0; //Reset busy with the reset signal?
    end else begin
        if (!Busy && something) begin
            //When not busy and something happens
            Busy <= 1'b1;
        end

        if (Busy && something_else) begin
            //When busy and something else happens
            Busy <= 1'b0;
        end
    end
end

Worth mentioning in the above it is fine having two separate if statements controlling the same register because it is quite clear that they will never both happen at the same time (one happens on !Busy the other on Busy so they are mutually exclusive).

You can also see here that I have used non-blocking statements. This is the preferred approach for always blocks. Where possible try to use non-blocking, using blocking assignments only in functions and tasks. There are some places where blocking can be useful, but more often than not there is no reason to use them.

If you were doing more stuff, you may find it easier to have it in an if-else format, such as:

if (!Busy) begin
   //Logic when not busy. E.g.
   if (something) begin
       Busy <= 1'b1;
   end
end else begin
   //Logic when busy. E.g.
   if (something_else) begin
       Busy <= 1'b0;
   end
end

Best Answer

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Electronic – FPGA design rules – Using a Module Output Register Value Internaly

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